1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HWIO_H 6 #define _DPU_HWIO_H 7 8 #include "dpu_hw_util.h" 9 10 /** 11 * MDP TOP block Register and bit fields and defines 12 */ 13 #define DISP_INTF_SEL 0x004 14 #define INTR_EN 0x010 15 #define INTR_STATUS 0x014 16 #define INTR_CLEAR 0x018 17 #define INTR2_EN 0x008 18 #define INTR2_STATUS 0x00c 19 #define SSPP_SPARE 0x028 20 #define INTR2_CLEAR 0x02c 21 #define HIST_INTR_EN 0x01c 22 #define HIST_INTR_STATUS 0x020 23 #define HIST_INTR_CLEAR 0x024 24 #define SPLIT_DISPLAY_EN 0x2F4 25 #define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8 26 #define DSPP_IGC_COLOR0_RAM_LUTN 0x300 27 #define DSPP_IGC_COLOR1_RAM_LUTN 0x304 28 #define DSPP_IGC_COLOR2_RAM_LUTN 0x308 29 #define DANGER_STATUS 0x360 30 #define SAFE_STATUS 0x364 31 #define HW_EVENTS_CTL 0x37C 32 #define MDP_WD_TIMER_0_CTL 0x380 33 #define MDP_WD_TIMER_0_CTL2 0x384 34 #define MDP_WD_TIMER_0_LOAD_VALUE 0x388 35 #define MDP_WD_TIMER_1_CTL 0x390 36 #define MDP_WD_TIMER_1_CTL2 0x394 37 #define MDP_WD_TIMER_1_LOAD_VALUE 0x398 38 #define CLK_CTRL3 0x3A8 39 #define CLK_STATUS3 0x3AC 40 #define CLK_CTRL4 0x3B0 41 #define CLK_STATUS4 0x3B4 42 #define CLK_CTRL5 0x3B8 43 #define CLK_STATUS5 0x3BC 44 #define CLK_CTRL7 0x3D0 45 #define CLK_STATUS7 0x3D4 46 #define SPLIT_DISPLAY_LOWER_PIPE_CTRL 0x3F0 47 #define SPLIT_DISPLAY_TE_LINE_INTERVAL 0x3F4 48 #define INTF_SW_RESET_MASK 0x3FC 49 #define HDMI_DP_CORE_SELECT 0x408 50 #define MDP_OUT_CTL_0 0x410 51 #define MDP_VSYNC_SEL 0x414 52 #define MDP_WD_TIMER_2_CTL 0x420 53 #define MDP_WD_TIMER_2_CTL2 0x424 54 #define MDP_WD_TIMER_2_LOAD_VALUE 0x428 55 #define MDP_WD_TIMER_3_CTL 0x430 56 #define MDP_WD_TIMER_3_CTL2 0x434 57 #define MDP_WD_TIMER_3_LOAD_VALUE 0x438 58 #define MDP_WD_TIMER_4_CTL 0x440 59 #define MDP_WD_TIMER_4_CTL2 0x444 60 #define MDP_WD_TIMER_4_LOAD_VALUE 0x448 61 #define DCE_SEL 0x450 62 63 #define MDP_DP_PHY_INTF_SEL 0x460 64 #define MDP_DP_PHY_INTF_SEL_INTF0 GENMASK(2, 0) 65 #define MDP_DP_PHY_INTF_SEL_INTF1 GENMASK(5, 3) 66 #define MDP_DP_PHY_INTF_SEL_PHY0 GENMASK(8, 6) 67 #define MDP_DP_PHY_INTF_SEL_PHY1 GENMASK(11, 9) 68 #define MDP_DP_PHY_INTF_SEL_PHY2 GENMASK(14, 12) 69 70 #define MDP_PERIPH_TOP0 MDP_WD_TIMER_0_CTL 71 #define MDP_PERIPH_TOP0_END CLK_CTRL3 72 73 #endif /*_DPU_HWIO_H */ 74