1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML_TOP_TYPES_H__ 6 #define __DML_TOP_TYPES_H__ 7 8 #include "dml_top_display_cfg_types.h" 9 #include "dml_top_soc_parameter_types.h" 10 #include "dml_top_policy_types.h" 11 #include "dml_top_dchub_registers.h" 12 13 #include "dmub_cmd.h" 14 15 struct dml2_instance; 16 17 enum dml2_status { 18 dml2_success = 0, 19 dml2_error_generic = 1 20 }; 21 22 enum dml2_project_id { 23 dml2_project_invalid = 0, 24 dml2_project_dcn4x_stage1 = 1, 25 dml2_project_dcn4x_stage2 = 2, 26 dml2_project_dcn4x_stage2_auto_drr_svp = 3, 27 }; 28 29 enum dml2_dram_clock_change_support { 30 dml2_dram_clock_change_vactive = 0, 31 dml2_dram_clock_change_vblank = 1, 32 dml2_dram_clock_change_vblank_and_vactive = 2, 33 dml2_dram_clock_change_drr = 3, 34 dml2_dram_clock_change_mall_svp = 4, 35 dml2_dram_clock_change_mall_full_frame = 6, 36 dml2_dram_clock_change_unsupported = 7 37 }; 38 39 enum dml2_fclock_change_support { 40 dml2_fclock_change_vactive = 0, 41 dml2_fclock_change_vblank = 1, 42 dml2_fclock_change_unsupported = 2 43 }; 44 45 enum dml2_output_type_and_rate__type { 46 dml2_output_type_unknown = 0, 47 dml2_output_type_dp = 1, 48 dml2_output_type_edp = 2, 49 dml2_output_type_dp2p0 = 3, 50 dml2_output_type_hdmi = 4, 51 dml2_output_type_hdmifrl = 5 52 }; 53 54 enum dml2_output_type_and_rate__rate { 55 dml2_output_rate_unknown = 0, 56 dml2_output_rate_dp_rate_hbr = 1, 57 dml2_output_rate_dp_rate_hbr2 = 2, 58 dml2_output_rate_dp_rate_hbr3 = 3, 59 dml2_output_rate_dp_rate_uhbr10 = 4, 60 dml2_output_rate_dp_rate_uhbr13p5 = 5, 61 dml2_output_rate_dp_rate_uhbr20 = 6, 62 dml2_output_rate_hdmi_rate_3x3 = 7, 63 dml2_output_rate_hdmi_rate_6x3 = 8, 64 dml2_output_rate_hdmi_rate_6x4 = 9, 65 dml2_output_rate_hdmi_rate_8x4 = 10, 66 dml2_output_rate_hdmi_rate_10x4 = 11, 67 dml2_output_rate_hdmi_rate_12x4 = 12 68 }; 69 70 struct dml2_pmo_options { 71 bool disable_vblank; 72 bool disable_svp; 73 bool disable_drr_var; 74 bool disable_drr_clamped; 75 bool disable_drr_var_when_var_active; 76 bool disable_drr_clamped_when_var_active; 77 bool disable_fams2; 78 bool disable_vactive_det_fill_bw_pad; /* dml2_project_dcn4x_stage2_auto_drr_svp and above only */ 79 bool disable_dyn_odm; 80 bool disable_dyn_odm_for_multi_stream; 81 bool disable_dyn_odm_for_stream_with_svp; 82 }; 83 84 struct dml2_options { 85 enum dml2_project_id project_id; 86 struct dml2_pmo_options pmo_options; 87 }; 88 89 struct dml2_initialize_instance_in_out { 90 struct dml2_instance *dml2_instance; 91 struct dml2_options options; 92 struct dml2_soc_bb soc_bb; 93 struct dml2_ip_capabilities ip_caps; 94 95 struct { 96 void *explicit_ip_bb; 97 unsigned int explicit_ip_bb_size; 98 } overrides; 99 }; 100 101 struct dml2_reset_instance_in_out { 102 struct dml2_instance *dml2_instance; 103 }; 104 105 struct dml2_check_mode_supported_in_out { 106 /* 107 * Inputs 108 */ 109 struct dml2_instance *dml2_instance; 110 const struct dml2_display_cfg *display_config; 111 112 /* 113 * Outputs 114 */ 115 bool is_supported; 116 }; 117 118 struct dml2_mcache_surface_allocation { 119 bool valid; 120 /* 121 * For iMALL, dedicated mall mcaches are required (sharing of last 122 * slice possible), for legacy phantom or phantom without return 123 * the only mall mcaches need to be valid. 124 */ 125 bool requires_dedicated_mall_mcache; 126 127 unsigned int num_mcaches_plane0; 128 unsigned int num_mcaches_plane1; 129 /* 130 * A plane is divided into vertical slices of mcaches, 131 * which wrap on the surface width. 132 * 133 * For example, if the surface width is 7680, and split into 134 * three slices of equal width, the boundary array would contain 135 * [2560, 5120, 7680] 136 * 137 * The assignments are 138 * 0 = [0 .. 2559] 139 * 1 = [2560 .. 5119] 140 * 2 = [5120 .. 7679] 141 * 0 = [7680 .. INF] 142 * The final element implicitly is the same as the first, and 143 * at first seems invalid since it is never referenced (since) 144 * it is outside the surface. However, its useful when shifting 145 * (see below). 146 * 147 * For any given valid mcache assignment, a shifted version, wrapped 148 * on the surface width boundary is also assumed to be valid. 149 * 150 * For example, shifting [2560, 5120, 7680] by -50 results in 151 * [2510, 5170, 7630]. 152 * 153 * The assignments are now: 154 * 0 = [0 .. 2509] 155 * 1 = [2510 .. 5169] 156 * 2 = [5170 .. 7629] 157 * 0 = [7630 .. INF] 158 */ 159 int mcache_x_offsets_plane0[DML2_MAX_MCACHES + 1]; 160 int mcache_x_offsets_plane1[DML2_MAX_MCACHES + 1]; 161 162 /* 163 * Shift grainularity is not necessarily 1 164 */ 165 struct { 166 int p0; 167 int p1; 168 } shift_granularity; 169 170 /* 171 * MCacheIDs have global scope in the SoC, and they are stored here. 172 * These IDs are generally not valid until all planes in a display 173 * configuration have had their mcache requirements calculated. 174 */ 175 int global_mcache_ids_plane0[DML2_MAX_MCACHES + 1]; 176 int global_mcache_ids_plane1[DML2_MAX_MCACHES + 1]; 177 int global_mcache_ids_mall_plane0[DML2_MAX_MCACHES + 1]; 178 int global_mcache_ids_mall_plane1[DML2_MAX_MCACHES + 1]; 179 180 /* 181 * Generally, plane0/1 slices must use a disjoint set of caches 182 * but in some cases the final segement of the two planes can 183 * use the same cache. If plane0_plane1 is set, then this is 184 * allowed. 185 * 186 * Similarly, the caches allocated to MALL prefetcher are generally 187 * disjoint, but if mall_prefetch is set, then the final segment 188 * between the main and the mall pixel requestor can use the same 189 * cache. 190 * 191 * Note that both bits may be set at the same time. 192 */ 193 struct { 194 bool mall_comb_mcache_p0; 195 bool mall_comb_mcache_p1; 196 bool plane0_plane1; 197 } last_slice_sharing; 198 199 struct { 200 int meta_row_bytes_plane0; 201 int meta_row_bytes_plane1; 202 } informative; 203 }; 204 205 enum dml2_uclk_pstate_support_method { 206 dml2_uclk_pstate_support_method_not_supported = 0, 207 /* hw */ 208 dml2_uclk_pstate_support_method_vactive = 1, 209 dml2_uclk_pstate_support_method_vblank = 2, 210 dml2_uclk_pstate_support_method_reserved_hw = 5, 211 /* fw */ 212 dml2_uclk_pstate_support_method_fw_subvp_phantom = 6, 213 dml2_uclk_pstate_support_method_reserved_fw = 10, 214 /* fw w/drr */ 215 dml2_uclk_pstate_support_method_fw_vactive_drr = 11, 216 dml2_uclk_pstate_support_method_fw_vblank_drr = 12, 217 dml2_uclk_pstate_support_method_fw_subvp_phantom_drr = 13, 218 dml2_uclk_pstate_support_method_reserved_fw_drr_fixed = 20, 219 dml2_uclk_pstate_support_method_fw_drr = 21, 220 dml2_uclk_pstate_support_method_reserved_fw_drr_var = 22, 221 222 dml2_uclk_pstate_support_method_count 223 }; 224 225 struct dml2_per_plane_programming { 226 const struct dml2_plane_parameters *plane_descriptor; 227 228 union { 229 struct { 230 unsigned long dppclk_khz; 231 } dcn4x; 232 } min_clocks; 233 234 struct dml2_mcache_surface_allocation mcache_allocation; 235 236 // If a stream is using automatic or forced odm combine 237 // and the stream for this plane has num_odms_required > 1 238 // num_dpps_required is always equal to num_odms_required for 239 // ALL planes of the stream 240 241 // If a stream is using odm split, then this value is always 1 242 unsigned int num_dpps_required; 243 244 enum dml2_uclk_pstate_support_method uclk_pstate_support_method; 245 246 // MALL size requirements for MALL SS and SubVP 247 unsigned int surface_size_mall_bytes; 248 unsigned int svp_size_mall_bytes; 249 250 struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES]; 251 252 struct { 253 bool valid; 254 struct dml2_plane_parameters descriptor; 255 struct dml2_dchub_per_pipe_register_set *pipe_regs[DML2_MAX_PLANES]; 256 } phantom_plane; 257 }; 258 259 union dml2_global_sync_programming { 260 struct { 261 unsigned int vstartup_lines; 262 unsigned int vupdate_offset_pixels; 263 unsigned int vupdate_vupdate_width_pixels; 264 unsigned int vready_offset_pixels; 265 unsigned int pstate_keepout_start_lines; 266 } dcn4x; 267 }; 268 269 struct dml2_per_stream_programming { 270 const struct dml2_stream_parameters *stream_descriptor; 271 272 union { 273 struct { 274 unsigned long dscclk_khz; 275 unsigned long dtbclk_khz; 276 unsigned long phyclk_khz; 277 } dcn4x; 278 } min_clocks; 279 280 union dml2_global_sync_programming global_sync; 281 282 unsigned int num_odms_required; 283 284 enum dml2_uclk_pstate_support_method uclk_pstate_method; 285 286 struct { 287 bool enabled; 288 struct dml2_stream_parameters descriptor; 289 union dml2_global_sync_programming global_sync; 290 } phantom_stream; 291 292 struct dmub_fams2_stream_static_state fams2_params; 293 }; 294 295 //----------------- 296 // Mode Support Information 297 //----------------- 298 299 struct dml2_mode_support_info { 300 bool ModeIsSupported; //<brief Is the mode support any voltage and combine setting 301 bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 302 // Mode Support Reason 303 bool WritebackLatencySupport; 304 bool ScaleRatioAndTapsSupport; 305 bool SourceFormatPixelAndScanSupport; 306 bool P2IWith420; 307 bool DSCOnlyIfNecessaryWithBPP; 308 bool DSC422NativeNotSupported; 309 bool LinkRateDoesNotMatchDPVersion; 310 bool LinkRateForMultistreamNotIndicated; 311 bool BPPForMultistreamNotIndicated; 312 bool MultistreamWithHDMIOreDP; 313 bool MSOOrODMSplitWithNonDPLink; 314 bool NotEnoughLanesForMSO; 315 bool NumberOfOTGSupport; 316 bool NumberOfHDMIFRLSupport; 317 bool NumberOfDP2p0Support; 318 bool WritebackScaleRatioAndTapsSupport; 319 bool CursorSupport; 320 bool PitchSupport; 321 bool ViewportExceedsSurface; 322 bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 323 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 324 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; 325 bool InvalidCombinationOfMALLUseForPState; 326 bool ExceededMALLSize; 327 bool EnoughWritebackUnits; 328 bool ExceededMultistreamSlots; 329 bool NotEnoughDSCUnits; 330 bool NotEnoughDSCSlices; 331 bool PixelsPerLinePerDSCUnitSupport; 332 bool DSCCLKRequiredMoreThanSupported; 333 bool DTBCLKRequiredMoreThanSupported; 334 bool LinkCapacitySupport; 335 bool ROBSupport; 336 bool OutstandingRequestsSupport; 337 bool OutstandingRequestsUrgencyAvoidance; 338 bool PTEBufferSizeNotExceeded; 339 bool DCCMetaBufferSizeNotExceeded; 340 bool TotalVerticalActiveBandwidthSupport; 341 bool VActiveBandwidthSupport; 342 enum dml2_fclock_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 343 bool USRRetrainingSupport; 344 bool PrefetchSupported; 345 bool DynamicMetadataSupported; 346 bool VRatioInPrefetchSupported; 347 bool DISPCLK_DPPCLK_Support; 348 bool TotalAvailablePipesSupport; 349 bool ViewportSizeSupport; 350 bool ImmediateFlipSupportedForState; 351 double MaxTotalVerticalActiveAvailableBandwidth; 352 bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 353 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 354 unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 355 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming 356 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required 357 unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode 358 double OutputBpp[DML2_MAX_PLANES]; 359 enum dml2_output_type_and_rate__type OutputType[DML2_MAX_PLANES]; 360 enum dml2_output_type_and_rate__rate OutputRate[DML2_MAX_PLANES]; 361 unsigned int AlignedYPitch[DML2_MAX_PLANES]; 362 unsigned int AlignedCPitch[DML2_MAX_PLANES]; 363 bool g6_temp_read_support; 364 }; // dml2_mode_support_info 365 366 struct dml2_display_cfg_programming { 367 struct dml2_display_cfg display_config; 368 369 union { 370 struct { 371 unsigned long dcfclk_khz; 372 unsigned long fclk_khz; 373 unsigned long uclk_khz; 374 unsigned long socclk_khz; 375 unsigned long dispclk_khz; 376 unsigned long dcfclk_deepsleep_khz; 377 unsigned long dpp_ref_khz; 378 } dcn32x; 379 struct { 380 struct { 381 unsigned long uclk_khz; 382 unsigned long fclk_khz; 383 unsigned long dcfclk_khz; 384 } active; 385 struct { 386 unsigned long uclk_khz; 387 unsigned long fclk_khz; 388 unsigned long dcfclk_khz; 389 } idle; 390 struct { 391 unsigned long uclk_khz; 392 unsigned long fclk_khz; 393 unsigned long dcfclk_khz; 394 } svp_prefetch; 395 396 unsigned long deepsleep_dcfclk_khz; 397 unsigned long dispclk_khz; 398 unsigned long dpprefclk_khz; 399 unsigned long dtbrefclk_khz; 400 unsigned long socclk_khz; 401 402 struct { 403 uint32_t dispclk_did; 404 uint32_t dpprefclk_did; 405 uint32_t dtbrefclk_did; 406 } divider_ids; 407 } dcn4x; 408 } min_clocks; 409 410 bool uclk_pstate_supported; 411 bool fclk_pstate_supported; 412 413 /* indicates this configuration requires FW to support */ 414 bool fams2_required; 415 struct dmub_cmd_fams2_global_config fams2_global_config; 416 417 struct { 418 bool supported_in_blank; // Changing to configurations where this is false requires stutter to be disabled during the transition 419 } stutter; 420 421 struct { 422 bool meets_eco; // Stutter cycles will meet Z8 ECO criteria 423 bool supported_in_blank; // Changing to configurations where this is false requires Z8 to be disabled during the transition 424 } z8_stutter; 425 426 struct dml2_dchub_global_register_set global_regs; 427 428 struct dml2_per_plane_programming plane_programming[DML2_MAX_PLANES]; 429 struct dml2_per_stream_programming stream_programming[DML2_MAX_PLANES]; 430 431 // Don't access this structure directly, access it through plane_programming.pipe_regs 432 struct dml2_dchub_per_pipe_register_set pipe_regs[DML2_MAX_PLANES]; 433 434 struct { 435 struct { 436 double urgent_us; 437 double writeback_urgent_us; 438 double writeback_pstate_us; 439 double writeback_fclk_pstate_us; 440 double cstate_exit_us; 441 double cstate_enter_plus_exit_us; 442 double z8_cstate_exit_us; 443 double z8_cstate_enter_plus_exit_us; 444 double pstate_change_us; 445 double fclk_pstate_change_us; 446 double usr_retraining_us; 447 double g6_temp_read_watermark_us; 448 } watermarks; 449 450 struct { 451 unsigned int swath_width_plane0; 452 unsigned int swath_height_plane0; 453 unsigned int swath_height_plane1; 454 unsigned int dpte_row_height_plane0; 455 unsigned int dpte_row_height_plane1; 456 unsigned int meta_row_height_plane0; 457 unsigned int meta_row_height_plane1; 458 } plane_info[DML2_MAX_PLANES]; 459 460 struct { 461 unsigned long long total_surface_size_in_mall_bytes; 462 unsigned int subviewport_lines_needed_in_mall[DML2_MAX_PLANES]; 463 } mall; 464 465 struct { 466 double urgent_latency_us; // urgent ramp latency 467 double max_non_urgent_latency_us; 468 double max_urgent_latency_us; 469 double avg_non_urgent_latency_us; 470 double avg_urgent_latency_us; 471 double wm_memory_trip_us; 472 double meta_trip_memory_us; 473 double fraction_of_urgent_bandwidth; // nom 474 double fraction_of_urgent_bandwidth_immediate_flip; 475 double fraction_of_urgent_bandwidth_mall; 476 double max_active_fclk_change_latency_supported; 477 unsigned int min_return_latency_in_dcfclk; 478 479 struct { 480 struct { 481 double sdp_bw_mbps; 482 double dram_bw_mbps; 483 double dram_vm_only_bw_mbps; 484 } svp_prefetch; 485 486 struct { 487 double sdp_bw_mbps; 488 double dram_bw_mbps; 489 double dram_vm_only_bw_mbps; 490 } sys_active; 491 } urg_bw_available; 492 493 struct { 494 struct { 495 double sdp_bw_mbps; 496 double dram_bw_mbps; 497 } svp_prefetch; 498 499 struct { 500 double sdp_bw_mbps; 501 double dram_bw_mbps; 502 } sys_active; 503 } avg_bw_available; 504 505 struct { 506 struct { 507 double sdp_bw_mbps; 508 double dram_bw_mbps; 509 } svp_prefetch; 510 511 struct { 512 double sdp_bw_mbps; 513 double dram_bw_mbps; 514 } sys_active; 515 } non_urg_bw_required; 516 517 struct { 518 struct { 519 double sdp_bw_mbps; 520 double dram_bw_mbps; 521 } svp_prefetch; 522 523 struct { 524 double sdp_bw_mbps; 525 double dram_bw_mbps; 526 } sys_active; 527 } non_urg_bw_required_with_flip; 528 529 struct { 530 struct { 531 double sdp_bw_mbps; 532 double dram_bw_mbps; 533 } svp_prefetch; 534 535 struct { 536 double sdp_bw_mbps; 537 double dram_bw_mbps; 538 } sys_active; 539 540 } urg_bw_required; 541 542 struct { 543 struct { 544 double sdp_bw_mbps; 545 double dram_bw_mbps; 546 } svp_prefetch; 547 548 struct { 549 double sdp_bw_mbps; 550 double dram_bw_mbps; 551 } sys_active; 552 } urg_bw_required_with_flip; 553 554 struct { 555 struct { 556 double sdp_bw_mbps; 557 double dram_bw_mbps; 558 } svp_prefetch; 559 560 struct { 561 double sdp_bw_mbps; 562 double dram_bw_mbps; 563 } sys_active; 564 } avg_bw_required; 565 } qos; 566 567 struct { 568 unsigned long long det_size_in_kbytes[DML2_MAX_PLANES]; 569 unsigned long long DETBufferSizeY[DML2_MAX_PLANES]; 570 unsigned long long comp_buffer_size_kbytes; 571 bool UnboundedRequestEnabled; 572 unsigned int compbuf_reserved_space_64b; 573 } crb; 574 575 struct { 576 unsigned int max_uncompressed_block_plane0; 577 unsigned int max_compressed_block_plane0; 578 unsigned int independent_block_plane0; 579 unsigned int max_uncompressed_block_plane1; 580 unsigned int max_compressed_block_plane1; 581 unsigned int independent_block_plane1; 582 } dcc_control[DML2_MAX_PLANES]; 583 584 struct { 585 double stutter_efficiency; 586 double stutter_efficiency_with_vblank; 587 double stutter_num_bursts; 588 589 struct { 590 double stutter_efficiency; 591 double stutter_efficiency_with_vblank; 592 double stutter_num_bursts; 593 double stutter_period; 594 595 struct { 596 double stutter_efficiency; 597 double stutter_num_bursts; 598 double stutter_period; 599 } bestcase; 600 } z8; 601 } power_management; 602 603 struct { 604 double min_ttu_vblank_us[DML2_MAX_PLANES]; 605 bool vready_at_or_after_vsync[DML2_MAX_PLANES]; 606 double min_dst_y_next_start[DML2_MAX_PLANES]; 607 bool cstate_max_cap_mode; 608 bool hw_debug5; 609 unsigned int dcfclk_deep_sleep_hysteresis; 610 unsigned int dst_x_after_scaler[DML2_MAX_PLANES]; 611 unsigned int dst_y_after_scaler[DML2_MAX_PLANES]; 612 unsigned int prefetch_source_lines_plane0[DML2_MAX_PLANES]; 613 unsigned int prefetch_source_lines_plane1[DML2_MAX_PLANES]; 614 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 615 bool UsesMALLForStaticScreen[DML2_MAX_PLANES]; 616 unsigned int CursorDstXOffset[DML2_MAX_PLANES]; 617 unsigned int CursorDstYOffset[DML2_MAX_PLANES]; 618 unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES]; 619 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 620 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 621 double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES]; 622 double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES]; 623 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 624 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 625 double TimePerVMGroupVBlank[DML2_MAX_PLANES]; 626 double TimePerVMGroupFlip[DML2_MAX_PLANES]; 627 double TimePerVMRequestVBlank[DML2_MAX_PLANES]; 628 double TimePerVMRequestFlip[DML2_MAX_PLANES]; 629 double Tdmdl_vm[DML2_MAX_PLANES]; 630 double Tdmdl[DML2_MAX_PLANES]; 631 unsigned int VStartup[DML2_MAX_PLANES]; 632 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 633 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 634 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 635 636 double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES]; 637 double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES]; 638 double time_per_pte_group_nom_luma[DML2_MAX_PLANES]; 639 double time_per_pte_group_nom_chroma[DML2_MAX_PLANES]; 640 double time_per_pte_group_vblank_luma[DML2_MAX_PLANES]; 641 double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES]; 642 double time_per_pte_group_flip_luma[DML2_MAX_PLANES]; 643 double time_per_pte_group_flip_chroma[DML2_MAX_PLANES]; 644 double VRatioPrefetchY[DML2_MAX_PLANES]; 645 double VRatioPrefetchC[DML2_MAX_PLANES]; 646 double DestinationLinesForPrefetch[DML2_MAX_PLANES]; 647 double DestinationLinesToRequestVMInVBlank[DML2_MAX_PLANES]; 648 double DestinationLinesToRequestRowInVBlank[DML2_MAX_PLANES]; 649 double DestinationLinesToRequestVMInImmediateFlip[DML2_MAX_PLANES]; 650 double DestinationLinesToRequestRowInImmediateFlip[DML2_MAX_PLANES]; 651 double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES]; 652 double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES]; 653 double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 654 double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 655 656 double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; 657 double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; 658 double DSCCLK_calculated[DML2_MAX_PLANES]; 659 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 660 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 661 double DSCDelay[DML2_MAX_PLANES]; 662 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 663 unsigned int PrefetchMode[DML2_MAX_PLANES]; // LEGACY_ONLY 664 bool ROBUrgencyAvoidance; 665 } misc; 666 667 struct dml2_mode_support_info mode_support_info; 668 unsigned int voltage_level; // LEGACY_ONLY 669 670 // For DV only 671 // This is what dml core calculated, only on the full_vp width and assume we have 672 // unlimited # of mcache 673 struct dml2_mcache_surface_allocation non_optimized_mcache_allocation[DML2_MAX_PLANES]; 674 675 bool failed_mcache_validation; 676 bool failed_dpmm; 677 bool failed_mode_programming; 678 } informative; 679 }; 680 681 struct dml2_build_mode_programming_in_out { 682 /* 683 * Inputs 684 */ 685 struct dml2_instance *dml2_instance; 686 const struct dml2_display_cfg *display_config; 687 688 /* 689 * Outputs 690 */ 691 struct dml2_display_cfg_programming *programming; 692 }; 693 694 struct dml2_build_mcache_programming_in_out { 695 /* 696 * Inputs 697 */ 698 struct dml2_instance *dml2_instance; 699 700 struct dml2_plane_mcache_configuration_descriptor mcache_configurations[DML2_MAX_PLANES]; 701 char num_configurations; 702 703 /* 704 * Outputs 705 */ 706 // per_plane_pipe_mcache_regs[i][j] refers to the proper programming for the j-th pipe of the 707 // i-th plane (from mcache_configurations) 708 struct dml2_hubp_pipe_mcache_regs *per_plane_pipe_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 709 710 // It's not a good idea to reference this directly, better to use the pointer structure above instead 711 struct dml2_hubp_pipe_mcache_regs mcache_regs_set[DML2_MAX_DCN_PIPES]; 712 }; 713 714 struct dml2_unit_test_in_out { 715 /* 716 * Inputs 717 */ 718 struct dml2_instance *dml2_instance; 719 }; 720 721 722 #endif 723