1 /*
2 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 /**
19 * DOC: wma_eht.c
20 *
21 * WLAN Host Device Driver 802.11be - Extremely High Throughput Implementation
22 */
23
24 #include "wma_eht.h"
25 #include "wmi_unified.h"
26 #include "service_ready_param.h"
27 #include "target_if.h"
28 #include "wma_internal.h"
29
30 #if defined(WLAN_FEATURE_11BE)
31 /* MCS Based EHT rate table */
32 /* MCS parameters with Nss = 1*/
33 static const struct index_eht_data_rate_type eht_mcs_nss1[] = {
34 /* MCS, {dcm0:0.8/1.6/3.2}, {dcm1:0.8/1.6/3.2} */
35 {0, {{86, 81, 73}, {0} }, /* EHT20 */
36 {{172, 163, 146}, {0} }, /* EHT40 */
37 {{360, 340, 306}, {0} }, /* EHT80 */
38 {{721, 681, 613}, {0} }, /* EHT160 */
39 {{1441, 1361, 1225}, {0}}} , /* EHT320 */
40 {1, {{172, 163, 146 }, {0} },
41 {{344, 325, 293 }, {0} },
42 {{721, 681, 613 }, {0} },
43 {{1441, 1361, 1225}, {0} },
44 {{2882, 2722, 2450}, {0} } } ,
45 {2, {{258, 244, 219 }, {0} },
46 {{516, 488, 439 }, {0} },
47 {{1081, 1021, 919 }, {0} },
48 {{2162, 2042, 1838}, {0} },
49 {{4324, 4083, 3675}, {0} } } ,
50 {3, {{344, 325, 293 }, {0} },
51 {{688, 650, 585 }, {0} },
52 {{1441, 1361, 1225}, {0} },
53 {{2882, 2722, 2450}, {0} },
54 {{5765, 5444, 4900}, {0} } } ,
55 {4, {{516, 488, 439 }, {0} },
56 {{1032, 975, 878 }, {0} },
57 {{2162, 2042, 1838}, {0} },
58 {{4324, 4083, 3675}, {0} },
59 {{8647, 8167, 7350}, {0} } } ,
60 {5, {{688, 650, 585 }, {0} },
61 {{1376, 1300, 1170}, {0} },
62 {{2882, 2722, 2450}, {0} },
63 {{5765, 5444, 4900}, {0} },
64 {{11529, 10889, 9800}, {0}}} ,
65 {6, {{774, 731, 658 }, {0} },
66 {{1549, 1463, 1316}, {0} },
67 {{3243, 3063, 2756}, {0} },
68 {{6485, 6125, 5513}, {0} },
69 {{12971, 12250, 11025}, {0} } } ,
70 {7, {{860, 813, 731 }, {0} },
71 {{1721, 1625, 1463}, {0} },
72 {{3603, 3403, 3063}, {0} },
73 {{7206, 6806, 6125}, {0} },
74 {{14412, 13611, 12250}, {0} } } ,
75 {8, {{1032, 975, 878 }, {0} },
76 {{2065, 1950, 1755}, {0} },
77 {{4324, 4083, 3675}, {0} },
78 {{8647, 8167, 7350}, {0} },
79 {{17294, 16333, 14700}, {0} }} ,
80 {9, {{1147, 1083, 975 }, {0} },
81 {{2294, 2167, 1950}, {0} },
82 {{4804, 4537, 4083}, {0} },
83 {{9608, 9074, 8167}, {0} },
84 {{19216, 18148, 16333}, {0} } } ,
85 {10, {{1290, 1219, 1097}, {0} },
86 {{2581, 2438, 2194}, {0} },
87 {{5404, 5104, 4594}, {0} },
88 {{10809, 10208, 9188}, {0} },
89 {{21618, 20417, 18375}, {0} } } ,
90 {11, {{1434, 1354, 1219}, {0} },
91 {{2868, 2708, 2438}, {0} },
92 {{6005, 5671, 5104}, {0} },
93 {{12010, 11342, 10208}, {0} },
94 {{24020, 22685, 20417}, {0} }} ,
95 {12, {{1549, 1463, 1316}, {0} },
96 {{3097, 2925, 2633}, {0} },
97 {{6485, 6125, 5513}, {0} },
98 {{12971, 12250, 11025}, {0} },
99 {{25941, 24500, 22050}, {0} }} ,
100 {13, {{1721, 1625, 1463}, {0} },
101 {{3441, 3250, 2925}, {0} },
102 {{7206, 6806, 6125}, {0} },
103 {{14412, 13611, 12250}, {0}},
104 {{28824, 27222, 24500}, {0}}} ,
105 };
106
107 /*MCS parameters with Nss = 2*/
108 static const struct index_eht_data_rate_type eht_mcs_nss2[] = {
109 /* MCS, {dcm0:0.8/1.6/3.2}, {dcm1:0.8/1.6/3.2} */
110 {0, {{172, 162, 146 }, {0} }, /* EHT20 */
111 {{344, 326, 292 }, {0} }, /* EHT40 */
112 {{720, 680, 612 }, {0} }, /* EHT80 */
113 {{1442, 1362, 1226}, {0} }, /* EHT160 */
114 {{2882, 2722, 2450}, {0} } } , /* EHT320 */
115 {1, {{344, 326, 292 }, {0} },
116 {{688, 650, 586 }, {0} },
117 {{1442, 1362, 1226}, {0} },
118 {{2882, 2722, 2450}, {0}},
119 {{5764, 5444, 4900}, {0} }} ,
120 {2, {{516, 488, 438 }, {0} },
121 {{1032, 976, 878 }, {0} },
122 {{2162, 2042, 1838}, {0} },
123 {{4324, 4084, 3676}, {0} },
124 {{8648, 8166, 7350}, {0} } } ,
125 {3, {{688, 650, 586 }, {0} },
126 {{1376, 1300, 1170}, {0} },
127 {{2882, 2722, 2450}, {0} },
128 {{5764, 5444, 4900}, {0} },
129 {{11530, 10888, 9800}, {0}} } ,
130 {4, {{1032, 976, 878 }, {0} },
131 {{2064, 1950, 1756}, {0} },
132 {{4324, 4083, 36756}, {0} },
133 {{8648, 8166, 7350}, {0} },
134 {{17294, 16334, 14700}, {0}}},
135 {5, {{1376, 1300, 1170}, {0} },
136 {{2752, 2600, 2340}, {0} },
137 {{5764, 5444, 4900}, {0} },
138 {{11530, 10888, 9800}, {0} },
139 {{23058, 21778, 19600}, {0} }} ,
140 {6, {{1548, 1462, 1316}, {0} },
141 {{3098, 2926, 2632}, {0} },
142 {{6486, 6126, 5512}, {0} },
143 {{12970, 12250, 11026}, {0} },
144 {{25942, 24500, 22050}, {0} }} ,
145 {7, {{1720, 1626, 1462}, {0} },
146 {{3442, 3250, 2926}, {0} },
147 {{7206, 6806, 61256}, {0} },
148 {{14412, 13612, 12250}, {0} },
149 {{28824, 27222, 24500}, {0} }} ,
150 {8, {{2064, 1950, 1756}, {0} },
151 {{4130, 3900, 3510}, {0} },
152 {{8648, 8166, 7350}, {0} },
153 {{17294, 16334, 14700}, {0} },
154 {{34588, 32666, 29400}, {0} }} ,
155 {9, {{2294, 2166, 1950}, {0} },
156 {{4588, 4334, 3900}, {0} },
157 {{9608, 9074, 8166}, {0} },
158 {{19216, 18148, 16334}, {0} },
159 {{38432, 36296, 32666}, {0} }} ,
160 {10, {{2580, 2438, 2194}, {0} },
161 {{5162, 4876, 4388}, {0} },
162 {{10808, 10208, 9188}, {0} },
163 {{21618, 20416, 18376}, {0} },
164 {{43236, 40834, 36750}, {0} }} ,
165 {11, {{2868, 2708, 2438}, {0} },
166 {{5736, 5416, 4876}, {0} },
167 {{12010, 11342, 10208}, {0} },
168 {{24020, 22686, 20416}, {0} },
169 {{48040, 45370, 40834}, {0} }} ,
170 {12, {{3098, 2926, 2632}, {0} },
171 {{6194, 5850, 5266}, {0} },
172 {{12970, 12250, 11026}, {0} },
173 {{25942, 24500, 22050}, {0} },
174 {{51882, 49000, 44100}, {0} }} ,
175 {13, {{3442, 3250, 2926}, {0} },
176 {{6882, 6500, 5850}, {0} },
177 {{14412, 13611, 12250}, {0} },
178 {{28824, 27222, 24500}, {0} },
179 {{57648, 54444, 49000}, {0} }}
180 };
181
182 /**
183 * wma_convert_eht_cap() - convert EHT capabilities into dot11f structure
184 * @eht_cap: pointer to dot11f structure
185 * @mac_cap: Received EHT MAC capability
186 * @phy_cap: Received EHT PHY capability
187 *
188 * This function converts various EHT capability received as part of extended
189 * service ready event into dot11f structure.
190 *
191 * Return: None
192 */
wma_convert_eht_cap(tDot11fIEeht_cap * eht_cap,uint32_t * mac_cap,uint32_t * phy_cap)193 static void wma_convert_eht_cap(tDot11fIEeht_cap *eht_cap, uint32_t *mac_cap,
194 uint32_t *phy_cap)
195 {
196 eht_cap->present = true;
197
198 /* EHT MAC capabilities */
199 eht_cap->epcs_pri_access = WMI_EHTCAP_MAC_NSEPPRIACCESS_GET(mac_cap);
200 eht_cap->eht_om_ctl = WMI_EHTCAP_MAC_EHTOMCTRL_GET(mac_cap);
201 eht_cap->triggered_txop_sharing_mode1 =
202 WMI_EHTCAP_MAC_TRIGTXOPMODE1_GET(mac_cap);
203 eht_cap->triggered_txop_sharing_mode2 =
204 WMI_EHTCAP_MAC_TRIGTXOPMODE2_GET(mac_cap);
205 eht_cap->restricted_twt = WMI_EHTCAP_MAC_RESTRICTTWT_GET(mac_cap);
206 eht_cap->scs_traffic_desc = WMI_EHTCAP_MAC_SCSTRAFFICDESC_GET(mac_cap);
207 eht_cap->max_mpdu_len = WMI_EHTCAP_MAC_MAXMPDULEN_GET(mac_cap);
208 eht_cap->max_a_mpdu_len_exponent_ext =
209 WMI_EHTCAP_MAC_MAXAMPDULEN_EXP_GET(mac_cap);
210 eht_cap->eht_trs_support =
211 WMI_EHTCAP_MAC_TRS_SUPPORT_GET(mac_cap);
212 eht_cap->txop_return_support_txop_share_m2 =
213 WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_GET(mac_cap);
214 eht_cap->two_bqrs_support =
215 WMI_EHTCAP_MAC_TWO_BQRS_SUPP_GET(mac_cap);
216 eht_cap->eht_link_adaptation_support =
217 WMI_EHTCAP_MAC_EHT_LINK_ADAPTATION_SUPP_GET(mac_cap);
218
219 /* EHT PHY capabilities */
220 eht_cap->support_320mhz_6ghz = WMI_EHTCAP_PHY_320MHZIN6GHZ_GET(phy_cap);
221 eht_cap->ru_242tone_wt_20mhz = WMI_EHTCAP_PHY_242TONERUBWLT20MHZ_GET(
222 phy_cap);
223 eht_cap->ndp_4x_eht_ltf_3dot2_us_gi =
224 WMI_EHTCAP_PHY_NDP4XEHTLTFAND320NSGI_GET(phy_cap);
225 eht_cap->partial_bw_mu_mimo = WMI_EHTCAP_PHY_PARTIALBWULMU_GET(phy_cap);
226 eht_cap->su_beamformer = WMI_EHTCAP_PHY_SUBFMR_GET(phy_cap);
227 eht_cap->su_beamformee = WMI_EHTCAP_PHY_SUBFME_GET(phy_cap);
228 eht_cap->bfee_ss_le_80mhz = WMI_EHTCAP_PHY_BFMESSLT80MHZ_GET(phy_cap);
229 eht_cap->bfee_ss_160mhz = WMI_EHTCAP_PHY_BFMESS160MHZ_GET(phy_cap);
230 eht_cap->bfee_ss_320mhz = WMI_EHTCAP_PHY_BFMESS320MHZ_GET(phy_cap);
231 eht_cap->num_sounding_dim_le_80mhz = WMI_EHTCAP_PHY_NUMSOUNDLT80MHZ_GET(
232 phy_cap);
233 eht_cap->num_sounding_dim_160mhz = WMI_EHTCAP_PHY_NUMSOUND160MHZ_GET(
234 phy_cap);
235 eht_cap->num_sounding_dim_320mhz = WMI_EHTCAP_PHY_NUMSOUND320MHZ_GET(
236 phy_cap);
237 eht_cap->ng_16_su_feedback = WMI_EHTCAP_PHY_NG16SUFB_GET(phy_cap);
238 eht_cap->ng_16_mu_feedback = WMI_EHTCAP_PHY_NG16MUFB_GET(phy_cap);
239 eht_cap->cb_sz_4_2_su_feedback = WMI_EHTCAP_PHY_CODBK42SUFB_GET(
240 phy_cap);
241 eht_cap->cb_sz_7_5_su_feedback = WMI_EHTCAP_PHY_CODBK75MUFB_GET(
242 phy_cap);
243 eht_cap->trig_su_bforming_feedback = WMI_EHTCAP_PHY_TRIGSUBFFB_GET(
244 phy_cap);
245 eht_cap->trig_mu_bforming_partial_bw_feedback =
246 WMI_EHTCAP_PHY_TRIGMUBFPARTBWFB_GET(phy_cap);
247 eht_cap->triggered_cqi_feedback = WMI_EHTCAP_PHY_TRIGCQIFB_GET(phy_cap);
248 eht_cap->partial_bw_dl_mu_mimo = WMI_EHTCAP_PHY_PARTBWDLMUMIMO_GET(
249 phy_cap);
250 eht_cap->psr_based_sr = WMI_EHTCAP_PHY_PSRSR_GET(phy_cap);
251 eht_cap->power_boost_factor = WMI_EHTCAP_PHY_PWRBSTFACTOR_GET(phy_cap);
252 eht_cap->eht_mu_ppdu_4x_ltf_0_8_us_gi =
253 WMI_EHTCAP_PHY_4XEHTLTFAND800NSGI_GET(phy_cap);
254 eht_cap->max_nc = WMI_EHTCAP_PHY_MAXNC_GET(phy_cap);
255 eht_cap->non_trig_cqi_feedback = WMI_EHTCAP_PHY_NONTRIGCQIFB_GET(
256 phy_cap);
257 eht_cap->tx_1024_4096_qam_lt_242_tone_ru =
258 WMI_EHTCAP_PHY_TX1024AND4096QAMLS242TONERU_GET(phy_cap);
259 eht_cap->rx_1024_4096_qam_lt_242_tone_ru =
260 WMI_EHTCAP_PHY_RX1024AND4096QAMLS242TONERU_GET(phy_cap);
261 eht_cap->ppet_present = WMI_EHTCAP_PHY_PPETHRESPRESENT_GET(phy_cap);
262 eht_cap->common_nominal_pkt_padding = WMI_EHTCAP_PHY_CMNNOMPKTPAD_GET(
263 phy_cap);
264 eht_cap->max_num_eht_ltf = WMI_EHTCAP_PHY_MAXNUMEHTLTF_GET(phy_cap);
265 eht_cap->mcs_15 = WMI_EHTCAP_PHY_SUPMCS15_GET(phy_cap);
266 eht_cap->eht_dup_6ghz = WMI_EHTCAP_PHY_EHTDUPIN6GHZ_GET(phy_cap);
267 eht_cap->op_sta_rx_ndp_wider_bw_20mhz =
268 WMI_EHTCAP_PHY_20MHZOPSTARXNDPWIDERBW_GET(phy_cap);
269 eht_cap->non_ofdma_ul_mu_mimo_le_80mhz =
270 WMI_EHTCAP_PHY_NONOFDMAULMUMIMOLT80MHZ_GET(phy_cap);
271 eht_cap->non_ofdma_ul_mu_mimo_160mhz =
272 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO160MHZ_GET(phy_cap);
273 eht_cap->non_ofdma_ul_mu_mimo_320mhz =
274 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO320MHZ_GET(phy_cap);
275 eht_cap->mu_bformer_le_80mhz = WMI_EHTCAP_PHY_MUBFMRLT80MHZ_GET(
276 phy_cap);
277 eht_cap->mu_bformer_160mhz = WMI_EHTCAP_PHY_MUBFMR160MHZ_GET(phy_cap);
278 eht_cap->mu_bformer_320mhz = WMI_EHTCAP_PHY_MUBFMR320MHZ_GET(phy_cap);
279 eht_cap->tb_sounding_feedback_rl =
280 WMI_EHTCAP_PHY_TBSUNDFBRATELIMIT_GET(phy_cap);
281 eht_cap->rx_1k_qam_in_wider_bw_dl_ofdma =
282 WMI_EHTCAP_PHY_RX1024QAMWIDERBWDLOFDMA_GET(phy_cap);
283 eht_cap->rx_4k_qam_in_wider_bw_dl_ofdma =
284 WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_GET(phy_cap);
285 eht_cap->limited_cap_support_20mhz =
286 WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_GET(phy_cap);
287 eht_cap->triggered_mu_bf_full_bw_fb_and_dl_mumimo =
288 WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(phy_cap);
289 eht_cap->mru_support_20mhz =
290 WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_GET(phy_cap);
291
292 /* TODO: MCS map and PPET */
293 }
294
wma_eht_update_tgt_services(struct wmi_unified * wmi_handle,struct wma_tgt_services * cfg)295 void wma_eht_update_tgt_services(struct wmi_unified *wmi_handle,
296 struct wma_tgt_services *cfg)
297 {
298 if (wmi_service_enabled(wmi_handle, wmi_service_11be)) {
299 cfg->en_11be = true;
300 wma_set_fw_wlan_feat_caps(DOT11BE);
301 wma_debug("11be is enabled");
302 } else {
303 cfg->en_11be = false;
304 wma_debug("11be is not enabled");
305 }
306 }
307
308 static void
wma_update_eht_cap_support_for_320mhz(struct target_psoc_info * tgt_hdl,tDot11fIEeht_cap * eht_cap)309 wma_update_eht_cap_support_for_320mhz(struct target_psoc_info *tgt_hdl,
310 tDot11fIEeht_cap *eht_cap)
311 {
312 struct wlan_psoc_host_mac_phy_caps_ext2 *cap;
313
314 cap = target_psoc_get_mac_phy_cap_ext2_for_mode(
315 tgt_hdl, WMI_HOST_HW_MODE_SINGLE);
316 if (!cap) {
317 wma_debug("HW_MODE_SINGLE does not exist");
318 return;
319 }
320
321 eht_cap->support_320mhz_6ghz = WMI_EHTCAP_PHY_320MHZIN6GHZ_GET(
322 cap->eht_cap_phy_info_5G);
323 eht_cap->max_num_eht_ltf =
324 WMI_EHTCAP_PHY_MAXNUMEHTLTF_GET(cap->eht_cap_phy_info_5G);
325 wma_debug("Support for 320MHz 0x%01x, max_num_eht_ltf %d",
326 eht_cap->support_320mhz_6ghz, eht_cap->max_num_eht_ltf);
327 }
328
329 static void
wma_update_eht_20mhz_only_mcs(uint32_t * mcs_2g_20,tDot11fIEeht_cap * eht_cap)330 wma_update_eht_20mhz_only_mcs(uint32_t *mcs_2g_20, tDot11fIEeht_cap *eht_cap)
331 {
332 eht_cap->bw_20_rx_max_nss_for_mcs_0_to_7 |= QDF_GET_BITS(*mcs_2g_20, 0, 4);
333 eht_cap->bw_20_tx_max_nss_for_mcs_0_to_7 |= QDF_GET_BITS(*mcs_2g_20, 4, 4);
334 eht_cap->bw_20_rx_max_nss_for_mcs_8_and_9 |= QDF_GET_BITS(*mcs_2g_20, 8, 4);
335 eht_cap->bw_20_tx_max_nss_for_mcs_8_and_9 |=
336 QDF_GET_BITS(*mcs_2g_20, 12, 4);
337 eht_cap->bw_20_rx_max_nss_for_mcs_10_and_11 |=
338 QDF_GET_BITS(*mcs_2g_20, 16, 4);
339 eht_cap->bw_20_tx_max_nss_for_mcs_10_and_11 |=
340 QDF_GET_BITS(*mcs_2g_20, 20, 4);
341 eht_cap->bw_20_rx_max_nss_for_mcs_12_and_13 |=
342 QDF_GET_BITS(*mcs_2g_20, 24, 4);
343 eht_cap->bw_20_tx_max_nss_for_mcs_12_and_13 |=
344 QDF_GET_BITS(*mcs_2g_20, 28, 4);
345 }
346
347 static void
wma_update_eht_le_80mhz_mcs(uint32_t * mcs_le_80,tDot11fIEeht_cap * eht_cap)348 wma_update_eht_le_80mhz_mcs(uint32_t *mcs_le_80, tDot11fIEeht_cap *eht_cap)
349 {
350 eht_cap->bw_le_80_rx_max_nss_for_mcs_0_to_9 |=
351 QDF_GET_BITS(*mcs_le_80, 0, 4);
352 eht_cap->bw_le_80_tx_max_nss_for_mcs_0_to_9 |=
353 QDF_GET_BITS(*mcs_le_80, 4, 4);
354 eht_cap->bw_le_80_rx_max_nss_for_mcs_10_and_11 |=
355 QDF_GET_BITS(*mcs_le_80, 8, 4);
356 eht_cap->bw_le_80_tx_max_nss_for_mcs_10_and_11 |=
357 QDF_GET_BITS(*mcs_le_80, 12, 4);
358 eht_cap->bw_le_80_rx_max_nss_for_mcs_12_and_13 |=
359 QDF_GET_BITS(*mcs_le_80, 16, 4);
360 eht_cap->bw_le_80_tx_max_nss_for_mcs_12_and_13 |=
361 QDF_GET_BITS(*mcs_le_80, 20, 4);
362 }
363
364 static void
wma_update_eht_160mhz_mcs(uint32_t * mcs_160mhz,tDot11fIEeht_cap * eht_cap)365 wma_update_eht_160mhz_mcs(uint32_t *mcs_160mhz, tDot11fIEeht_cap *eht_cap)
366 {
367 eht_cap->bw_160_rx_max_nss_for_mcs_0_to_9 |=
368 QDF_GET_BITS(*mcs_160mhz, 0, 4);
369 eht_cap->bw_160_tx_max_nss_for_mcs_0_to_9 |=
370 QDF_GET_BITS(*mcs_160mhz, 4, 4);
371 eht_cap->bw_160_rx_max_nss_for_mcs_10_and_11 |=
372 QDF_GET_BITS(*mcs_160mhz, 8, 4);
373 eht_cap->bw_160_tx_max_nss_for_mcs_10_and_11 |=
374 QDF_GET_BITS(*mcs_160mhz, 12, 4);
375 eht_cap->bw_160_rx_max_nss_for_mcs_12_and_13 |=
376 QDF_GET_BITS(*mcs_160mhz, 16, 4);
377 eht_cap->bw_160_tx_max_nss_for_mcs_12_and_13 |=
378 QDF_GET_BITS(*mcs_160mhz, 20, 4);
379 }
380
381 static void
wma_update_eht_320mhz_mcs(uint32_t * mcs_320mhz,tDot11fIEeht_cap * eht_cap)382 wma_update_eht_320mhz_mcs(uint32_t *mcs_320mhz, tDot11fIEeht_cap *eht_cap)
383 {
384 eht_cap->bw_320_rx_max_nss_for_mcs_0_to_9 |=
385 QDF_GET_BITS(*mcs_320mhz, 0, 4);
386 eht_cap->bw_320_tx_max_nss_for_mcs_0_to_9 |=
387 QDF_GET_BITS(*mcs_320mhz, 4, 4);
388 eht_cap->bw_320_rx_max_nss_for_mcs_10_and_11 |=
389 QDF_GET_BITS(*mcs_320mhz, 8, 4);
390 eht_cap->bw_320_tx_max_nss_for_mcs_10_and_11 |=
391 QDF_GET_BITS(*mcs_320mhz, 12, 4);
392 eht_cap->bw_320_rx_max_nss_for_mcs_12_and_13 |=
393 QDF_GET_BITS(*mcs_320mhz, 16, 4);
394 eht_cap->bw_320_tx_max_nss_for_mcs_12_and_13 |=
395 QDF_GET_BITS(*mcs_320mhz, 20, 4);
396 }
397
wma_update_target_ext_eht_cap(struct target_psoc_info * tgt_hdl,struct wma_tgt_cfg * tgt_cfg)398 void wma_update_target_ext_eht_cap(struct target_psoc_info *tgt_hdl,
399 struct wma_tgt_cfg *tgt_cfg)
400 {
401 tDot11fIEeht_cap *eht_cap = &tgt_cfg->eht_cap;
402 tDot11fIEeht_cap *eht_cap_2g = &tgt_cfg->eht_cap_2g;
403 tDot11fIEeht_cap *eht_cap_5g = &tgt_cfg->eht_cap_5g;
404 int i, num_hw_modes, total_mac_phy_cnt;
405 tDot11fIEeht_cap eht_cap_mac;
406 struct wlan_psoc_host_mac_phy_caps_ext2 *mac_phy_cap, *mac_phy_caps2;
407 struct wlan_psoc_host_mac_phy_caps *host_cap;
408 uint32_t supported_bands;
409 uint32_t *mcs_supp;
410
411 qdf_mem_zero(eht_cap_2g, sizeof(tDot11fIEeht_cap));
412 qdf_mem_zero(eht_cap_5g, sizeof(tDot11fIEeht_cap));
413 num_hw_modes = target_psoc_get_num_hw_modes(tgt_hdl);
414 mac_phy_cap = target_psoc_get_mac_phy_cap_ext2(tgt_hdl);
415 host_cap = target_psoc_get_mac_phy_cap(tgt_hdl);
416 total_mac_phy_cnt = target_psoc_get_total_mac_phy_cnt(tgt_hdl);
417 if (!mac_phy_cap || !host_cap) {
418 wma_err("Invalid MAC PHY capabilities handle");
419 eht_cap->present = false;
420 return;
421 }
422
423 if (!num_hw_modes) {
424 wma_err("No extended EHT cap for current SOC");
425 eht_cap->present = false;
426 return;
427 }
428
429 if (!tgt_cfg->services.en_11be) {
430 wma_info("Target does not support 11BE");
431 eht_cap->present = false;
432 return;
433 }
434
435 for (i = 0; i < total_mac_phy_cnt; i++) {
436 supported_bands = host_cap[i].supported_bands;
437 qdf_mem_zero(&eht_cap_mac, sizeof(tDot11fIEeht_cap));
438 mac_phy_caps2 = &mac_phy_cap[i];
439 if (supported_bands & WLAN_2G_CAPABILITY) {
440 wma_convert_eht_cap(&eht_cap_mac,
441 mac_phy_caps2->eht_cap_info_2G,
442 mac_phy_caps2->eht_cap_phy_info_2G);
443 /* TODO: PPET */
444 /* WMI_EHT_SUPP_MCS_20MHZ_ONLY */
445 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_2G[0];
446 wma_update_eht_20mhz_only_mcs(mcs_supp, &eht_cap_mac);
447 /* WMI_EHT_SUPP_MCS_LE_80MHZ */
448 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_2G[1];
449 wma_update_eht_le_80mhz_mcs(mcs_supp, &eht_cap_mac);
450
451 qdf_mem_copy(eht_cap_2g, &eht_cap_mac,
452 sizeof(tDot11fIEeht_cap));
453 }
454
455 if (supported_bands & WLAN_5G_CAPABILITY) {
456 qdf_mem_zero(&eht_cap_mac, sizeof(tDot11fIEeht_cap));
457 wma_convert_eht_cap(&eht_cap_mac,
458 mac_phy_caps2->eht_cap_info_5G,
459 mac_phy_caps2->eht_cap_phy_info_5G);
460
461 /* WMI_EHT_SUPP_MCS_20MHZ_ONLY */
462 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[0];
463 wma_update_eht_20mhz_only_mcs(mcs_supp, &eht_cap_mac);
464 /* WMI_EHT_SUPP_MCS_LE_80MHZ */
465 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[1];
466 wma_update_eht_le_80mhz_mcs(mcs_supp, &eht_cap_mac);
467
468 /* WMI_EHT_SUPP_MCS_160MHZ */
469 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[2];
470 wma_update_eht_160mhz_mcs(mcs_supp, &eht_cap_mac);
471 /* WMI_EHT_SUPP_MCS_320MHZ */
472 mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[3];
473 wma_update_eht_320mhz_mcs(mcs_supp, &eht_cap_mac);
474
475 qdf_mem_copy(eht_cap_5g, &eht_cap_mac,
476 sizeof(tDot11fIEeht_cap));
477 }
478 }
479 qdf_mem_copy(eht_cap, &eht_cap_mac, sizeof(tDot11fIEeht_cap));
480
481 wma_update_eht_cap_support_for_320mhz(tgt_hdl, eht_cap);
482 wma_update_eht_cap_support_for_320mhz(tgt_hdl, eht_cap_5g);
483
484 wma_print_eht_cap(eht_cap);
485 }
486
wma_update_vdev_eht_ops(uint32_t * eht_ops,tDot11fIEeht_op * eht_op)487 void wma_update_vdev_eht_ops(uint32_t *eht_ops, tDot11fIEeht_op *eht_op)
488 {
489 }
490
wma_print_eht_cap(tDot11fIEeht_cap * eht_cap)491 void wma_print_eht_cap(tDot11fIEeht_cap *eht_cap)
492 {
493 if (!eht_cap->present)
494 return;
495
496 wma_debug("EHT Caps: EPCS PA 0x%01x OM ctl 0x%01x Triggered TXOP Sharing mode1:0x%01x mode2:0x%01x, Restricted TWT 0x%01x SCS Traffic Desc 0x%01x Max MPDU 0x%01x Max A-MPDU exponent ext: 0x%01x",
497 eht_cap->epcs_pri_access, eht_cap->eht_om_ctl,
498 eht_cap->triggered_txop_sharing_mode1,
499 eht_cap->triggered_txop_sharing_mode2,
500 eht_cap->restricted_twt, eht_cap->scs_traffic_desc,
501 eht_cap->max_mpdu_len,
502 eht_cap->max_a_mpdu_len_exponent_ext);
503 wma_nofl_debug(" TRS supp 0x%01x TXOP return support in TXOP M2 0x%01x Two BQRs supp 0x%01x EHT link adaptation supp 0x%01x 320MHz 6GHz 0x%01x 242-tone RU WT 20 MHz 0x%01x NDP_4x EHT-LTF 3.2 us GI 0x%01x",
504 eht_cap->eht_trs_support,
505 eht_cap->txop_return_support_txop_share_m2,
506 eht_cap->two_bqrs_support,
507 eht_cap->eht_link_adaptation_support,
508 eht_cap->support_320mhz_6ghz,
509 eht_cap->ru_242tone_wt_20mhz,
510 eht_cap->ndp_4x_eht_ltf_3dot2_us_gi);
511 wma_nofl_debug(" Partial BW UL MU-MIMO: 0x%01x, SU: Bfer 0x%01x Bfee 0x%01x, Bfee SS: LE 80Mhz 0x%03x 160Mhz 0x%03x 320Mhz 0x%03x, No. of Sounding Dim LE 80Mhz 0x%03x 160Mhz 0x%03x 320Mhz 0x%03x ",
512 eht_cap->partial_bw_mu_mimo,
513 eht_cap->su_beamformer, eht_cap->su_beamformee,
514 eht_cap->bfee_ss_le_80mhz, eht_cap->bfee_ss_160mhz,
515 eht_cap->bfee_ss_320mhz,
516 eht_cap->num_sounding_dim_le_80mhz,
517 eht_cap->num_sounding_dim_160mhz,
518 eht_cap->num_sounding_dim_320mhz);
519 wma_nofl_debug(" Ng 16: SU Feedback 0x%01x, MU Feedback 0x%01x Codebook: 4 2 SU: 0x%01x, 7 5 MU: 0x%01x, Trig SU Bfing fb 0x%01x, MU Bfing partial BW 0x%01x Trig CQI FB 0x%01x, Part BW DL MU-MIMO: 0x%01x",
520 eht_cap->ng_16_su_feedback, eht_cap->ng_16_mu_feedback,
521 eht_cap->cb_sz_4_2_su_feedback,
522 eht_cap->cb_sz_7_5_su_feedback,
523 eht_cap->trig_su_bforming_feedback,
524 eht_cap->trig_mu_bforming_partial_bw_feedback,
525 eht_cap->triggered_cqi_feedback,
526 eht_cap->partial_bw_dl_mu_mimo);
527 wma_nofl_debug(" PSR-Based SR 0x%01x, Power Boost Factor 0x%01x, MU PPDU With 4x EHT-LTF 0.8 us GI 0x%01x Max Nc: 0x%04x, Non-Trig CQI FB 0x%01x, 1024-QAM 4096-QAM < 242-tone RU: TX 0x%01x RX 0x%01x",
528 eht_cap->psr_based_sr, eht_cap->power_boost_factor,
529 eht_cap->eht_mu_ppdu_4x_ltf_0_8_us_gi,
530 eht_cap->max_nc, eht_cap->non_trig_cqi_feedback,
531 eht_cap->tx_1024_4096_qam_lt_242_tone_ru,
532 eht_cap->rx_1024_4096_qam_lt_242_tone_ru);
533 wma_nofl_debug(" PPE Thresholds 0x%01x, Common Nominal Pkt Padding 0x%02x, Max No. Sup EHT-LTFs 0x%05x, MCS 15 0x%04x, DUP 6 GHz 0x%01x, 20 MHz STA RX NDP With Wider BW 0x%01x",
534 eht_cap->ppet_present,
535 eht_cap->common_nominal_pkt_padding,
536 eht_cap->max_num_eht_ltf, eht_cap->mcs_15,
537 eht_cap->eht_dup_6ghz,
538 eht_cap->op_sta_rx_ndp_wider_bw_20mhz);
539 wma_nofl_debug(" Non-OFDMA ULMU: LE 80MHz 0x%01x 160MHz 0x%01x 320MHz 0x%01x, MUBfmer: LE 80MHz 0x%01x 160MHz 0x%01x 320MHz 0x%01x, TB sound FBRL 0x%01x, WBDL OFDMA Rx: 1024QAM 0x%01x 4096QAM 0x%01x",
540 eht_cap->non_ofdma_ul_mu_mimo_le_80mhz,
541 eht_cap->non_ofdma_ul_mu_mimo_160mhz,
542 eht_cap->non_ofdma_ul_mu_mimo_320mhz,
543 eht_cap->mu_bformer_le_80mhz,
544 eht_cap->mu_bformer_160mhz, eht_cap->mu_bformer_320mhz,
545 eht_cap->tb_sounding_feedback_rl,
546 eht_cap->rx_1k_qam_in_wider_bw_dl_ofdma,
547 eht_cap->rx_4k_qam_in_wider_bw_dl_ofdma);
548 wma_nofl_debug(" 20 MHz-Only: Limited Cap 0x%01x Triggered MU Bfing Full BW FB, DL MU-MIMO 0x%01x M-RU Support 0x%01x, EHT MCS: 20MHz::: 0-7: RX: 0x%x TX: 0x%x, 8-9: RX: 0x%x TX: 0x%x",
549 eht_cap->limited_cap_support_20mhz,
550 eht_cap->triggered_mu_bf_full_bw_fb_and_dl_mumimo,
551 eht_cap->mru_support_20mhz,
552 eht_cap->bw_20_rx_max_nss_for_mcs_0_to_7,
553 eht_cap->bw_20_tx_max_nss_for_mcs_0_to_7,
554 eht_cap->bw_20_rx_max_nss_for_mcs_8_and_9,
555 eht_cap->bw_20_tx_max_nss_for_mcs_8_and_9);
556 wma_nofl_debug(" 20MHz::: 10-11: RX: 0x%x TX: 0x%x, 12-13: RX: 0x%x TX: 0x%x, 80Mhz LE::: 0-9: RX: 0x%x TX: 0x%x, 10-11: RX: 0x%x TX: 0x%x, 12-13: RX: 0x%x TX: 0x%x",
557 eht_cap->bw_20_rx_max_nss_for_mcs_10_and_11,
558 eht_cap->bw_20_tx_max_nss_for_mcs_10_and_11,
559 eht_cap->bw_20_rx_max_nss_for_mcs_12_and_13,
560 eht_cap->bw_20_tx_max_nss_for_mcs_12_and_13,
561 eht_cap->bw_le_80_rx_max_nss_for_mcs_0_to_9,
562 eht_cap->bw_le_80_tx_max_nss_for_mcs_0_to_9,
563 eht_cap->bw_le_80_rx_max_nss_for_mcs_10_and_11,
564 eht_cap->bw_le_80_tx_max_nss_for_mcs_10_and_11,
565 eht_cap->bw_le_80_rx_max_nss_for_mcs_12_and_13,
566 eht_cap->bw_le_80_tx_max_nss_for_mcs_12_and_13);
567 wma_nofl_debug(" 160Mhz::: 0-9: RX: 0x%x TX: 0x%x, 10-11: RX: 0x%x TX: 0x%x, 12-13: RX: 0x%x TX: 0x%x, 320Mhz::: 0-9: RX: 0x%x TX: 0x%x, 10-11: RX: 0x%x TX: 0x%x, 12-13: RX: 0x%x TX: 0x%x",
568 eht_cap->bw_160_rx_max_nss_for_mcs_0_to_9,
569 eht_cap->bw_160_tx_max_nss_for_mcs_0_to_9,
570 eht_cap->bw_160_rx_max_nss_for_mcs_10_and_11,
571 eht_cap->bw_160_tx_max_nss_for_mcs_10_and_11,
572 eht_cap->bw_160_rx_max_nss_for_mcs_12_and_13,
573 eht_cap->bw_160_tx_max_nss_for_mcs_12_and_13,
574 eht_cap->bw_320_rx_max_nss_for_mcs_0_to_9,
575 eht_cap->bw_320_tx_max_nss_for_mcs_0_to_9,
576 eht_cap->bw_320_rx_max_nss_for_mcs_10_and_11,
577 eht_cap->bw_320_tx_max_nss_for_mcs_10_and_11,
578 eht_cap->bw_320_rx_max_nss_for_mcs_12_and_13,
579 eht_cap->bw_320_tx_max_nss_for_mcs_12_and_13);
580 }
581
wma_print_eht_phy_cap(uint32_t * phy_cap)582 void wma_print_eht_phy_cap(uint32_t *phy_cap)
583 {
584 wma_debug("EHT PHY Cap: 320 MHz In 6 GHz 0x%01x, 242-tone RU In BW Wider Than 20 MHz 0x%01x, NDP With 4x EHT-LTF And 3.2 us GI 0x%01x, Partial BW UL MU-MIMO 0x%01x",
585 WMI_EHTCAP_PHY_320MHZIN6GHZ_GET(phy_cap),
586 WMI_EHTCAP_PHY_242TONERUBWLT20MHZ_GET(phy_cap),
587 WMI_EHTCAP_PHY_NDP4XEHTLTFAND320NSGI_GET(phy_cap),
588 WMI_EHTCAP_PHY_PARTIALBWULMU_GET(phy_cap));
589 wma_nofl_debug(" SU: Bfmer 0x%01x Bfmee 0x%01x, Bfmee SS: LE 80MHz 0x%03x 160MHz 0x%03x 320MHz 0x%03x, No. of Sounding Dim: LE 80MHz 0x%03x 160MHz 0x%03x 320MHz 0x%03x",
590 WMI_EHTCAP_PHY_SUBFMR_GET(phy_cap),
591 WMI_EHTCAP_PHY_SUBFME_GET(phy_cap),
592 WMI_EHTCAP_PHY_BFMESSLT80MHZ_GET(phy_cap),
593 WMI_EHTCAP_PHY_BFMESS160MHZ_GET(phy_cap),
594 WMI_EHTCAP_PHY_BFMESS320MHZ_GET(phy_cap),
595 WMI_EHTCAP_PHY_NUMSOUNDLT80MHZ_GET(phy_cap),
596 WMI_EHTCAP_PHY_NUMSOUND160MHZ_GET(phy_cap),
597 WMI_EHTCAP_PHY_NUMSOUND320MHZ_GET(phy_cap));
598 wma_nofl_debug(" Ng 16 FB: SU 0x%01x MU 0x%01x, Codebook Size: 42 SU FB 0x%01x 75 MU FB: 0x%01x, Trigg SU Bfming FB 0x%01x, MU Bfming Partial BW FB 0x%01x",
599 WMI_EHTCAP_PHY_NG16SUFB_GET(phy_cap),
600 WMI_EHTCAP_PHY_NG16MUFB_GET(phy_cap),
601 WMI_EHTCAP_PHY_CODBK42SUFB_GET(phy_cap),
602 WMI_EHTCAP_PHY_CODBK75MUFB_GET(phy_cap),
603 WMI_EHTCAP_PHY_TRIGSUBFFB_GET(phy_cap),
604 WMI_EHTCAP_PHY_TRIGMUBFPARTBWFB_GET(phy_cap));
605 wma_nofl_debug(" Triggered CQI FB 0x%01x, Partial BW DL MU-MIMO 0x%01x, PSR-Based SR 0x%01x, Power Boost Factor 0x%01x, MU PPDU 4x EHT-LTF 0.8 us GI 0x%01x",
606 WMI_EHTCAP_PHY_TRIGCQIFB_GET(phy_cap),
607 WMI_EHTCAP_PHY_TRIGMUBFPARTBWFB_GET(phy_cap),
608 WMI_EHTCAP_PHY_PSRSR_GET(phy_cap),
609 WMI_EHTCAP_PHY_PWRBSTFACTOR_GET(phy_cap),
610 WMI_EHTCAP_PHY_4XEHTLTFAND800NSGI_GET(phy_cap));
611 wma_nofl_debug(" Max Nc 0x%04x, Non-Triggered CQI FB 0x%01x, 1024-QAM 4096-QAM < 242-tone RU: TX 0x%01x RX 0x%01x, PPE Thresholds 0x%01x, Common Nominal Packet Padding 0x%02x",
612 WMI_EHTCAP_PHY_MAXNC_GET(phy_cap),
613 WMI_EHTCAP_PHY_NONTRIGCQIFB_GET(phy_cap),
614 WMI_EHTCAP_PHY_TX1024AND4096QAMLS242TONERU_GET(phy_cap),
615 WMI_EHTCAP_PHY_RX1024AND4096QAMLS242TONERU_GET(phy_cap),
616 WMI_EHTCAP_PHY_PPETHRESPRESENT_GET(phy_cap),
617 WMI_EHTCAP_PHY_CMNNOMPKTPAD_GET(phy_cap));
618 wma_nofl_debug(" Max No. Supp LTFs 0x%05x, MCS 15 0x%04x, EHT DUP 6 GHz 0x%01x, 20MHz STA RX NDP Wider BW 0x%01x, Non-OFDMA UL MU-MIMO: LE 80MHz 0x%01x 160 MHz 0x%01x 320Mhz 0x%01x",
619 WMI_EHTCAP_PHY_MAXNUMEHTLTF_GET(phy_cap),
620 WMI_EHTCAP_PHY_SUPMCS15_GET(phy_cap),
621 WMI_EHTCAP_PHY_EHTDUPIN6GHZ_GET(phy_cap),
622 WMI_EHTCAP_PHY_20MHZOPSTARXNDPWIDERBW_GET(phy_cap),
623 WMI_EHTCAP_PHY_NONOFDMAULMUMIMOLT80MHZ_GET(phy_cap),
624 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO160MHZ_GET(phy_cap),
625 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO320MHZ_GET(phy_cap));
626 wma_nofl_debug(" MUBfmer: LE 80MHz 0x%01x 160MHz 0x%01x 320Mhz 0x%01x, TB sound FBRL 0x%01x, WBW DLOFDMA Rx: 1024QAM 0x%01x 4096QAM 0x%01x, 20MHz: Lim Cap 0x%01x Trig MUBfing BWFB DLMU 0x%01x M-RU 0x%01x",
627 WMI_EHTCAP_PHY_MUBFMRLT80MHZ_GET(phy_cap),
628 WMI_EHTCAP_PHY_MUBFMR160MHZ_GET(phy_cap),
629 WMI_EHTCAP_PHY_MUBFMR320MHZ_GET(phy_cap),
630 WMI_EHTCAP_PHY_TBSUNDFBRATELIMIT_GET(phy_cap),
631 WMI_EHTCAP_PHY_RX1024QAMWIDERBWDLOFDMA_GET(phy_cap),
632 WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_GET(phy_cap),
633 WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_GET(phy_cap),
634 WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(phy_cap),
635 WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_GET(phy_cap));
636 }
637
wma_print_eht_mac_cap(uint32_t * mac_cap)638 void wma_print_eht_mac_cap(uint32_t *mac_cap)
639 {
640 wma_debug("EHT MAC Cap: EPCS Priority Access: 0x%01x OM Control: 0x%01x, Trig TXOP Sharing: mode1 0x%01x mode2 0x%01x, Restricted TWT 0x%01x SCS Traffic Desc 0x%01x",
641 WMI_EHTCAP_MAC_EPCSPRIACCESS_GET(mac_cap),
642 WMI_EHTCAP_MAC_EHTOMCTRL_GET(mac_cap),
643 WMI_EHTCAP_MAC_TRIGTXOPMODE1_GET(mac_cap),
644 WMI_EHTCAP_MAC_TRIGTXOPMODE2_GET(mac_cap),
645 WMI_EHTCAP_MAC_RESTRICTTWT_GET(mac_cap),
646 WMI_EHTCAP_MAC_SCSTRAFFICDESC_GET(mac_cap));
647 wma_nofl_debug(" Max MPDU len 0x%01x, Max A-MPDU Len Exponent Ext 0x%01x EHT TRS 0x%01x, OP In TXOP Sharing Mode2 0x%01x, Two BQRs 0x%01x, EHT Link Adaptation 0x%01x",
648 WMI_EHTCAP_MAC_MAXMPDULEN_GET(mac_cap),
649 WMI_EHTCAP_MAC_MAXAMPDULEN_EXP_GET(mac_cap),
650 WMI_EHTCAP_MAC_TRS_SUPPORT_GET(mac_cap),
651 WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_GET(mac_cap),
652 WMI_EHTCAP_MAC_TWO_BQRS_SUPP_GET(mac_cap),
653 WMI_EHTCAP_MAC_EHT_LINK_ADAPTATION_SUPP_GET(mac_cap));
654 }
655
wma_print_eht_op(tDot11fIEeht_op * eht_ops)656 void wma_print_eht_op(tDot11fIEeht_op *eht_ops)
657 {
658 }
659
wma_populate_peer_eht_cap(struct peer_assoc_params * peer,tpAddStaParams params)660 void wma_populate_peer_eht_cap(struct peer_assoc_params *peer,
661 tpAddStaParams params)
662 {
663 tDot11fIEeht_cap *eht_cap = ¶ms->eht_config;
664 uint32_t *phy_cap = peer->peer_eht_cap_phyinfo;
665 uint32_t *mac_cap = peer->peer_eht_cap_macinfo;
666 struct supported_rates *rates;
667
668 if (!params->eht_capable)
669 return;
670
671 peer->eht_flag = 1;
672 peer->qos_flag = 1;
673
674 /* EHT MAC Capabilities */
675 WMI_EHTCAP_MAC_EPCSPRIACCESS_SET(mac_cap, eht_cap->epcs_pri_access);
676 WMI_EHTCAP_MAC_EHTOMCTRL_SET(mac_cap, eht_cap->eht_om_ctl);
677 WMI_EHTCAP_MAC_TRIGTXOPMODE1_SET(mac_cap,
678 eht_cap->triggered_txop_sharing_mode1);
679 WMI_EHTCAP_MAC_TRIGTXOPMODE2_SET(mac_cap,
680 eht_cap->triggered_txop_sharing_mode2);
681 WMI_EHTCAP_MAC_RESTRICTTWT_SET(mac_cap,
682 eht_cap->restricted_twt);
683 WMI_EHTCAP_MAC_SCSTRAFFICDESC_SET(mac_cap,
684 eht_cap->scs_traffic_desc);
685 WMI_EHTCAP_MAC_MAXMPDULEN_SET(mac_cap,
686 eht_cap->max_mpdu_len);
687 WMI_EHTCAP_MAC_MAXAMPDULEN_EXP_SET(mac_cap,
688 eht_cap->max_a_mpdu_len_exponent_ext);
689 WMI_EHTCAP_MAC_TRS_SUPPORT_SET(mac_cap,
690 eht_cap->eht_trs_support);
691 WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_SET(mac_cap,
692 eht_cap->txop_return_support_txop_share_m2);
693 WMI_EHTCAP_MAC_TWO_BQRS_SUPP_SET(mac_cap,
694 eht_cap->two_bqrs_support);
695 WMI_EHTCAP_MAC_EHT_LINK_ADAPTATION_SUPP_SET(mac_cap,
696 eht_cap->eht_link_adaptation_support);
697
698 /* EHT PHY Capabilities */
699 WMI_EHTCAP_PHY_320MHZIN6GHZ_SET(phy_cap, eht_cap->support_320mhz_6ghz);
700 WMI_EHTCAP_PHY_242TONERUBWLT20MHZ_SET(phy_cap,
701 eht_cap->ru_242tone_wt_20mhz);
702 WMI_EHTCAP_PHY_NDP4XEHTLTFAND320NSGI_SET(
703 phy_cap, eht_cap->ndp_4x_eht_ltf_3dot2_us_gi);
704 WMI_EHTCAP_PHY_PARTIALBWULMU_SET(phy_cap, eht_cap->partial_bw_mu_mimo);
705 WMI_EHTCAP_PHY_SUBFMR_SET(phy_cap, eht_cap->su_beamformer);
706 WMI_EHTCAP_PHY_SUBFME_SET(phy_cap, eht_cap->su_beamformee);
707 WMI_EHTCAP_PHY_BFMESSLT80MHZ_SET(phy_cap, eht_cap->bfee_ss_le_80mhz);
708 WMI_EHTCAP_PHY_BFMESS160MHZ_SET(phy_cap, eht_cap->bfee_ss_160mhz);
709 WMI_EHTCAP_PHY_BFMESS320MHZ_SET(phy_cap, eht_cap->bfee_ss_320mhz);
710 WMI_EHTCAP_PHY_NUMSOUNDLT80MHZ_SET(
711 phy_cap, eht_cap->num_sounding_dim_le_80mhz);
712 WMI_EHTCAP_PHY_NUMSOUND160MHZ_SET(phy_cap,
713 eht_cap->num_sounding_dim_160mhz);
714 WMI_EHTCAP_PHY_NUMSOUND320MHZ_SET(phy_cap,
715 eht_cap->num_sounding_dim_320mhz);
716 WMI_EHTCAP_PHY_NG16SUFB_SET(phy_cap, eht_cap->ng_16_su_feedback);
717 WMI_EHTCAP_PHY_NG16MUFB_SET(phy_cap, eht_cap->ng_16_mu_feedback);
718 WMI_EHTCAP_PHY_CODBK42SUFB_SET(phy_cap, eht_cap->cb_sz_4_2_su_feedback);
719 WMI_EHTCAP_PHY_CODBK75MUFB_SET(phy_cap, eht_cap->cb_sz_7_5_su_feedback);
720 WMI_EHTCAP_PHY_TRIGSUBFFB_SET(phy_cap,
721 eht_cap->trig_su_bforming_feedback);
722 WMI_EHTCAP_PHY_TRIGMUBFPARTBWFB_SET(
723 phy_cap, eht_cap->trig_mu_bforming_partial_bw_feedback);
724 WMI_EHTCAP_PHY_TRIGCQIFB_SET(phy_cap, eht_cap->triggered_cqi_feedback);
725 WMI_EHTCAP_PHY_PARTBWDLMUMIMO_SET(phy_cap,
726 eht_cap->partial_bw_dl_mu_mimo);
727 WMI_EHTCAP_PHY_PSRSR_SET(phy_cap, eht_cap->psr_based_sr);
728 WMI_EHTCAP_PHY_PWRBSTFACTOR_SET(phy_cap, eht_cap->power_boost_factor);
729 WMI_EHTCAP_PHY_4XEHTLTFAND800NSGI_SET(
730 phy_cap, eht_cap->eht_mu_ppdu_4x_ltf_0_8_us_gi);
731 WMI_EHTCAP_PHY_MAXNC_SET(phy_cap, eht_cap->max_nc);
732 WMI_EHTCAP_PHY_NONTRIGCQIFB_SET(phy_cap,
733 eht_cap->non_trig_cqi_feedback);
734 WMI_EHTCAP_PHY_TX1024AND4096QAMLS242TONERU_SET(
735 phy_cap, eht_cap->tx_1024_4096_qam_lt_242_tone_ru);
736 WMI_EHTCAP_PHY_RX1024AND4096QAMLS242TONERU_SET(
737 phy_cap, eht_cap->rx_1024_4096_qam_lt_242_tone_ru);
738 WMI_EHTCAP_PHY_PPETHRESPRESENT_SET(phy_cap, eht_cap->ppet_present);
739 WMI_EHTCAP_PHY_CMNNOMPKTPAD_SET(phy_cap,
740 eht_cap->common_nominal_pkt_padding);
741 WMI_EHTCAP_PHY_MAXNUMEHTLTF_SET(phy_cap, eht_cap->max_num_eht_ltf);
742 WMI_EHTCAP_PHY_SUPMCS15_SET(phy_cap, eht_cap->mcs_15);
743 WMI_EHTCAP_PHY_EHTDUPIN6GHZ_SET(phy_cap, eht_cap->eht_dup_6ghz);
744 WMI_EHTCAP_PHY_20MHZOPSTARXNDPWIDERBW_SET(
745 phy_cap, eht_cap->op_sta_rx_ndp_wider_bw_20mhz);
746 WMI_EHTCAP_PHY_NONOFDMAULMUMIMOLT80MHZ_SET(
747 phy_cap, eht_cap->non_ofdma_ul_mu_mimo_le_80mhz);
748 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO160MHZ_SET(
749 phy_cap, eht_cap->non_ofdma_ul_mu_mimo_160mhz);
750 WMI_EHTCAP_PHY_NONOFDMAULMUMIMO320MHZ_SET(
751 phy_cap, eht_cap->non_ofdma_ul_mu_mimo_320mhz);
752 WMI_EHTCAP_PHY_MUBFMRLT80MHZ_SET(phy_cap, eht_cap->mu_bformer_le_80mhz);
753 WMI_EHTCAP_PHY_MUBFMR160MHZ_SET(phy_cap, eht_cap->mu_bformer_160mhz);
754 WMI_EHTCAP_PHY_MUBFMR320MHZ_SET(phy_cap, eht_cap->mu_bformer_320mhz);
755 WMI_EHTCAP_PHY_TBSUNDFBRATELIMIT_SET(phy_cap,
756 eht_cap->tb_sounding_feedback_rl);
757 WMI_EHTCAP_PHY_RX1024QAMWIDERBWDLOFDMA_SET(phy_cap,
758 eht_cap->rx_1k_qam_in_wider_bw_dl_ofdma);
759 WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(phy_cap,
760 eht_cap->rx_4k_qam_in_wider_bw_dl_ofdma);
761 WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_SET(phy_cap,
762 eht_cap->limited_cap_support_20mhz);
763 WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(phy_cap,
764 eht_cap->triggered_mu_bf_full_bw_fb_and_dl_mumimo);
765 WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_SET(phy_cap,
766 eht_cap->mru_support_20mhz);
767
768 peer->peer_eht_mcs_count = 0;
769 rates = ¶ms->supportedRates;
770
771 /*
772 * Convert eht mcs to firmware understandable format
773 * BITS 0:3 indicates support for mcs 0 to 7
774 * BITS 4:7 indicates support for mcs 8 and 9
775 * BITS 8:11 indicates support for mcs 10 and 11
776 * BITS 12:15 indicates support for mcs 12 and 13
777 */
778 switch (params->ch_width) {
779 case CH_WIDTH_320MHZ:
780 peer->peer_eht_mcs_count++;
781 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
782 0, 4, rates->bw_320_rx_max_nss_for_mcs_0_to_9);
783 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
784 0, 4, rates->bw_320_tx_max_nss_for_mcs_0_to_9);
785 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
786 4, 4, rates->bw_320_rx_max_nss_for_mcs_0_to_9);
787 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
788 4, 4, rates->bw_320_tx_max_nss_for_mcs_0_to_9);
789 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
790 8, 4, rates->bw_320_rx_max_nss_for_mcs_10_and_11);
791 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
792 8, 4, rates->bw_320_tx_max_nss_for_mcs_10_and_11);
793 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
794 12, 4, rates->bw_320_rx_max_nss_for_mcs_12_and_13);
795 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
796 12, 4, rates->bw_320_tx_max_nss_for_mcs_12_and_13);
797 fallthrough;
798 case CH_WIDTH_160MHZ:
799 peer->peer_eht_mcs_count++;
800 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
801 0, 4, rates->bw_160_rx_max_nss_for_mcs_0_to_9);
802 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
803 0, 4, rates->bw_160_tx_max_nss_for_mcs_0_to_9);
804 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
805 4, 4, rates->bw_160_rx_max_nss_for_mcs_0_to_9);
806 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
807 4, 4, rates->bw_160_tx_max_nss_for_mcs_0_to_9);
808 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
809 8, 4, rates->bw_160_rx_max_nss_for_mcs_10_and_11);
810 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
811 8, 4, rates->bw_160_rx_max_nss_for_mcs_10_and_11);
812 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
813 12, 4, rates->bw_160_rx_max_nss_for_mcs_12_and_13);
814 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
815 12, 4, rates->bw_160_tx_max_nss_for_mcs_12_and_13);
816 fallthrough;
817 case CH_WIDTH_80MHZ:
818 case CH_WIDTH_40MHZ:
819 peer->peer_eht_mcs_count++;
820 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
821 0, 4, rates->bw_le_80_rx_max_nss_for_mcs_0_to_9);
822 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
823 0, 4, rates->bw_le_80_tx_max_nss_for_mcs_0_to_9);
824 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
825 4, 4, rates->bw_le_80_rx_max_nss_for_mcs_0_to_9);
826 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
827 4, 4, rates->bw_le_80_tx_max_nss_for_mcs_0_to_9);
828 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
829 8, 4, rates->bw_le_80_rx_max_nss_for_mcs_10_and_11);
830 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
831 8, 4, rates->bw_le_80_tx_max_nss_for_mcs_10_and_11);
832 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
833 12, 4, rates->bw_le_80_rx_max_nss_for_mcs_12_and_13);
834 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
835 12, 4, rates->bw_le_80_rx_max_nss_for_mcs_12_and_13);
836 break;
837 case CH_WIDTH_20MHZ:
838 peer->peer_eht_mcs_count++;
839 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
840 0, 4, rates->bw_20_rx_max_nss_for_mcs_0_to_7);
841 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
842 0, 4, rates->bw_20_tx_max_nss_for_mcs_0_to_7);
843 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
844 4, 4, rates->bw_20_rx_max_nss_for_mcs_8_and_9);
845 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
846 4, 4, rates->bw_20_tx_max_nss_for_mcs_8_and_9);
847 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
848 8, 4, rates->bw_20_rx_max_nss_for_mcs_10_and_11);
849 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
850 8, 4, rates->bw_20_tx_max_nss_for_mcs_10_and_11);
851 QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
852 12, 4, rates->bw_20_rx_max_nss_for_mcs_12_and_13);
853 QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
854 12, 4, rates->bw_20_tx_max_nss_for_mcs_12_and_13);
855 break;
856 default:
857 break;
858 }
859
860 wma_print_eht_cap(eht_cap);
861 wma_debug("Peer EHT Capabilities:");
862 wma_print_eht_phy_cap(phy_cap);
863 wma_print_eht_mac_cap(mac_cap);
864 }
865
wma_vdev_set_eht_bss_params(tp_wma_handle wma,uint8_t vdev_id,struct vdev_mlme_eht_ops_info * eht_info)866 void wma_vdev_set_eht_bss_params(tp_wma_handle wma, uint8_t vdev_id,
867 struct vdev_mlme_eht_ops_info *eht_info)
868 {
869 if (!eht_info->eht_ops)
870 return;
871 }
872
wma_get_eht_capabilities(struct eht_capability * eht_cap)873 QDF_STATUS wma_get_eht_capabilities(struct eht_capability *eht_cap)
874 {
875 tp_wma_handle wma_handle;
876
877 wma_handle = cds_get_context(QDF_MODULE_ID_WMA);
878 if (!wma_handle)
879 return QDF_STATUS_E_FAILURE;
880
881 qdf_mem_copy(eht_cap->phy_cap,
882 &wma_handle->eht_cap.phy_cap,
883 WMI_MAX_EHTCAP_PHY_SIZE);
884 eht_cap->mac_cap = wma_handle->eht_cap.mac_cap;
885 return QDF_STATUS_SUCCESS;
886 }
887
wma_set_peer_assoc_params_bw_320(struct peer_assoc_params * params,enum phy_ch_width ch_width)888 void wma_set_peer_assoc_params_bw_320(struct peer_assoc_params *params,
889 enum phy_ch_width ch_width)
890 {
891 if (ch_width == CH_WIDTH_320MHZ)
892 params->bw_320 = 1;
893 }
894
wma_set_eht_txbf_cfg(struct mac_context * mac,uint8_t vdev_id)895 void wma_set_eht_txbf_cfg(struct mac_context *mac, uint8_t vdev_id)
896 {
897 wma_set_eht_txbf_params(
898 vdev_id, mac->mlme_cfg->eht_caps.dot11_eht_cap.su_beamformer,
899 mac->mlme_cfg->eht_caps.dot11_eht_cap.su_beamformee,
900 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_le_80mhz ||
901 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_160mhz ||
902 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_320mhz);
903 }
904
wma_set_eht_txbf_params(uint8_t vdev_id,bool su_bfer,bool su_bfee,bool mu_bfer)905 void wma_set_eht_txbf_params(uint8_t vdev_id, bool su_bfer,
906 bool su_bfee, bool mu_bfer)
907 {
908 uint32_t ehtmu_mode = 0;
909 QDF_STATUS status;
910 tp_wma_handle wma = cds_get_context(QDF_MODULE_ID_WMA);
911
912 if (!wma)
913 return;
914
915 if (su_bfer)
916 WMI_VDEV_EHT_SUBFER_ENABLE(ehtmu_mode);
917 if (su_bfee) {
918 WMI_VDEV_EHT_SUBFEE_ENABLE(ehtmu_mode);
919 WMI_VDEV_EHT_MUBFEE_ENABLE(ehtmu_mode);
920 }
921 if (mu_bfer)
922 WMI_VDEV_EHT_MUBFER_ENABLE(ehtmu_mode);
923
924 WMI_VDEV_EHT_DLOFDMA_ENABLE(ehtmu_mode);
925 WMI_VDEV_EHT_ULOFDMA_ENABLE(ehtmu_mode);
926
927 status = wma_vdev_set_param(wma->wmi_handle, vdev_id,
928 wmi_vdev_param_set_eht_mu_mode, ehtmu_mode);
929 wma_debug("set EHTMU_MODE (ehtmu_mode = 0x%x)", ehtmu_mode);
930
931 if (QDF_IS_STATUS_ERROR(status))
932 wma_err("failed to set EHTMU_MODE(status = %d)", status);
933 }
934
wma_set_bss_rate_flags_eht(enum tx_rate_info * rate_flags,struct bss_params * add_bss)935 QDF_STATUS wma_set_bss_rate_flags_eht(enum tx_rate_info *rate_flags,
936 struct bss_params *add_bss)
937 {
938 if (!add_bss->eht_capable)
939 return QDF_STATUS_E_NOSUPPORT;
940
941 *rate_flags |= wma_get_eht_rate_flags(add_bss->ch_width);
942
943 wma_debug("ehe_capable %d rate_flags 0x%x", add_bss->eht_capable,
944 *rate_flags);
945 return QDF_STATUS_SUCCESS;
946 }
947
wma_get_bss_eht_capable(struct bss_params * add_bss)948 bool wma_get_bss_eht_capable(struct bss_params *add_bss)
949 {
950 return add_bss->eht_capable;
951 }
952
wma_get_eht_rate_flags(enum phy_ch_width ch_width)953 enum tx_rate_info wma_get_eht_rate_flags(enum phy_ch_width ch_width)
954 {
955 enum tx_rate_info rate_flags = 0;
956
957 if (ch_width == CH_WIDTH_320MHZ)
958 rate_flags |= TX_RATE_EHT320 | TX_RATE_EHT160 |
959 TX_RATE_EHT80 | TX_RATE_EHT40 | TX_RATE_EHT20;
960 else if (ch_width == CH_WIDTH_160MHZ || ch_width == CH_WIDTH_80P80MHZ)
961 rate_flags |= TX_RATE_EHT160 | TX_RATE_EHT80 | TX_RATE_EHT40 |
962 TX_RATE_EHT20;
963 else if (ch_width == CH_WIDTH_80MHZ)
964 rate_flags |= TX_RATE_EHT80 | TX_RATE_EHT40 | TX_RATE_EHT20;
965 else if (ch_width)
966 rate_flags |= TX_RATE_EHT40 | TX_RATE_EHT20;
967 else
968 rate_flags |= TX_RATE_EHT20;
969
970 return rate_flags;
971 }
972
wma_match_eht_rate(uint16_t raw_rate,enum tx_rate_info rate_flags,uint8_t * nss,uint8_t * dcm,enum txrate_gi * guard_interval,enum tx_rate_info * mcs_rate_flag,uint8_t * p_index)973 uint16_t wma_match_eht_rate(uint16_t raw_rate,
974 enum tx_rate_info rate_flags,
975 uint8_t *nss, uint8_t *dcm,
976 enum txrate_gi *guard_interval,
977 enum tx_rate_info *mcs_rate_flag,
978 uint8_t *p_index)
979 {
980 uint8_t index;
981 uint8_t dcm_index_max = 1;
982 uint8_t dcm_index;
983 uint16_t match_rate = 0;
984 const uint16_t *nss1_rate;
985 const uint16_t *nss2_rate;
986
987 *p_index = 0;
988 if (!(rate_flags & (TX_RATE_EHT320 | TX_RATE_EHT160 | TX_RATE_EHT80 |
989 TX_RATE_EHT40 | TX_RATE_EHT20)))
990 return 0;
991
992 for (index = 0; index < QDF_ARRAY_SIZE(eht_mcs_nss1); index++) {
993 dcm_index_max = IS_MCS_HAS_DCM_RATE(index) ? 2 : 1;
994 for (dcm_index = 0; dcm_index < dcm_index_max; dcm_index++) {
995 if (rate_flags & TX_RATE_EHT320) {
996 nss1_rate = &eht_mcs_nss1[index].supported_eht320_rate[dcm_index][0];
997 nss2_rate = &eht_mcs_nss2[index].supported_eht320_rate[dcm_index][0];
998 match_rate = wma_mcs_rate_match(raw_rate, 1,
999 nss1_rate,
1000 nss2_rate,
1001 nss,
1002 guard_interval);
1003 if (match_rate)
1004 goto rate_found;
1005 }
1006 if (rate_flags & TX_RATE_EHT160) {
1007 nss1_rate = &eht_mcs_nss1[index].supported_eht160_rate[dcm_index][0];
1008 nss2_rate = &eht_mcs_nss2[index].supported_eht160_rate[dcm_index][0];
1009 match_rate = wma_mcs_rate_match(raw_rate, 1,
1010 nss1_rate,
1011 nss2_rate,
1012 nss,
1013 guard_interval);
1014 if (match_rate)
1015 goto rate_found;
1016 }
1017
1018 if (rate_flags & (TX_RATE_EHT80 | TX_RATE_EHT160)) {
1019 nss1_rate = &eht_mcs_nss1[index].supported_eht80_rate[dcm_index][0];
1020 nss2_rate = &eht_mcs_nss2[index].supported_eht80_rate[dcm_index][0];
1021 /* check for he80 nss1/2 rate set */
1022 match_rate = wma_mcs_rate_match(raw_rate, 1,
1023 nss1_rate,
1024 nss2_rate,
1025 nss,
1026 guard_interval);
1027 if (match_rate) {
1028 *mcs_rate_flag &= ~TX_RATE_EHT160;
1029 goto rate_found;
1030 }
1031 }
1032
1033 if (rate_flags & (TX_RATE_EHT40 | TX_RATE_EHT80 |
1034 TX_RATE_EHT160)) {
1035 nss1_rate = &eht_mcs_nss1[index].supported_eht40_rate[dcm_index][0];
1036 nss2_rate = &eht_mcs_nss2[index].supported_eht40_rate[dcm_index][0];
1037 match_rate = wma_mcs_rate_match(raw_rate, 1,
1038 nss1_rate,
1039 nss2_rate,
1040 nss,
1041 guard_interval);
1042
1043 if (match_rate) {
1044 *mcs_rate_flag &= ~(TX_RATE_EHT80 |
1045 TX_RATE_EHT160);
1046 goto rate_found;
1047 }
1048 }
1049
1050 if (rate_flags & (TX_RATE_EHT80 | TX_RATE_EHT40 |
1051 TX_RATE_EHT20 | TX_RATE_EHT160)) {
1052 nss1_rate = &eht_mcs_nss1[index].supported_eht20_rate[dcm_index][0];
1053 nss2_rate = &eht_mcs_nss2[index].supported_eht20_rate[dcm_index][0];
1054 match_rate = wma_mcs_rate_match(raw_rate, 1,
1055 nss1_rate,
1056 nss2_rate,
1057 nss,
1058 guard_interval);
1059
1060 if (match_rate) {
1061 *mcs_rate_flag &= TX_RATE_EHT20;
1062 goto rate_found;
1063 }
1064 }
1065 }
1066 }
1067
1068 rate_found:
1069 if (match_rate) {
1070 if (dcm_index == 1)
1071 *dcm = 1;
1072 *p_index = index;
1073 }
1074 return match_rate;
1075 }
1076
1077 QDF_STATUS
wma_set_eht_txbf_vdev_params(struct mac_context * mac,uint32_t * mode)1078 wma_set_eht_txbf_vdev_params(struct mac_context *mac, uint32_t *mode)
1079 {
1080 uint32_t ehtmu_mode = 0;
1081 bool su_bfer = mac->mlme_cfg->eht_caps.dot11_eht_cap.su_beamformer;
1082 bool su_bfee = mac->mlme_cfg->eht_caps.dot11_eht_cap.su_beamformee;
1083 bool mu_bfer =
1084 (mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_le_80mhz ||
1085 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_160mhz ||
1086 mac->mlme_cfg->eht_caps.dot11_eht_cap.mu_bformer_320mhz);
1087
1088 if (su_bfer)
1089 WMI_VDEV_EHT_SUBFER_ENABLE(ehtmu_mode);
1090 if (su_bfee) {
1091 WMI_VDEV_EHT_SUBFEE_ENABLE(ehtmu_mode);
1092 WMI_VDEV_EHT_MUBFEE_ENABLE(ehtmu_mode);
1093 }
1094 if (mu_bfer)
1095 WMI_VDEV_EHT_MUBFER_ENABLE(ehtmu_mode);
1096 WMI_VDEV_EHT_DLOFDMA_ENABLE(ehtmu_mode);
1097 WMI_VDEV_EHT_ULOFDMA_ENABLE(ehtmu_mode);
1098 wma_debug("set EHTMU_MODE (ehtmu_mode = 0x%x)",
1099 ehtmu_mode);
1100 *mode = ehtmu_mode;
1101
1102 return QDF_STATUS_SUCCESS;
1103 }
1104 #endif
1105
1106 #ifdef WLAN_FEATURE_11BE_MLO
wma_vdev_set_listen_interval(uint8_t vdev_id,uint8_t val)1107 void wma_vdev_set_listen_interval(uint8_t vdev_id, uint8_t val)
1108 {
1109 tp_wma_handle wma = cds_get_context(QDF_MODULE_ID_WMA);
1110 QDF_STATUS status;
1111
1112 status = wma_vdev_set_param(wma->wmi_handle, vdev_id,
1113 wmi_vdev_param_listen_interval, val);
1114 if (QDF_IS_STATUS_ERROR(status))
1115 wma_err("failed to set Listen interval for vdev: %d", vdev_id);
1116 }
1117 #endif
1118