1// SPDX-License-Identifier: GPL-2.0 2#include "bcm283x.dtsi" 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/soc/bcm2835-pm.h> 6 7/ { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 vc4: gpu { 16 compatible = "brcm,bcm2711-vc5"; 17 status = "disabled"; 18 }; 19 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <27000000>; 24 clock-output-names = "27MHz-clock"; 25 }; 26 27 clk_108MHz: clk-108M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <108000000>; 31 clock-output-names = "108MHz-clock"; 32 }; 33 34 soc { 35 /* 36 * Defined ranges: 37 * Common BCM283x peripherals 38 * BCM2711-specific peripherals 39 * ARM-local peripherals 40 */ 41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 42 <0x7c000000 0x0 0xfc000000 0x02000000>, 43 <0x40000000 0x0 0xff800000 0x00800000>; 44 /* Emulate a contiguous 30-bit address range for DMA */ 45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 46 47 /* 48 * This node is the provider for the enable-method for 49 * bringing up secondary cores. 50 */ 51 local_intc: interrupt-controller@40000000 { 52 compatible = "brcm,bcm2836-l1-intc"; 53 reg = <0x40000000 0x100>; 54 }; 55 56 gicv2: interrupt-controller@40041000 { 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "arm,gic-400"; 60 reg = <0x40041000 0x1000>, 61 <0x40042000 0x2000>, 62 <0x40044000 0x2000>, 63 <0x40046000 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 65 IRQ_TYPE_LEVEL_HIGH)>; 66 }; 67 68 avs_monitor: avs-monitor@7d5d2000 { 69 compatible = "brcm,bcm2711-avs-monitor", 70 "syscon", "simple-mfd"; 71 reg = <0x7d5d2000 0xf00>; 72 73 thermal: thermal { 74 compatible = "brcm,bcm2711-thermal"; 75 #thermal-sensor-cells = <0>; 76 }; 77 }; 78 79 dma: dma-controller@7e007000 { 80 compatible = "brcm,bcm2835-dma"; 81 reg = <0x7e007000 0xb00>; 82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 89 /* DMA lite 7 - 10 */ 90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-names = "dma0", 95 "dma1", 96 "dma2", 97 "dma3", 98 "dma4", 99 "dma5", 100 "dma6", 101 "dma7", 102 "dma8", 103 "dma9", 104 "dma10"; 105 #dma-cells = <1>; 106 brcm,dma-channel-mask = <0x07f5>; 107 }; 108 109 pm: watchdog@7e100000 { 110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; 111 #power-domain-cells = <1>; 112 #reset-cells = <1>; 113 reg = <0x7e100000 0x114>, 114 <0x7e00a000 0x24>, 115 <0x7ec11000 0x20>; 116 reg-names = "pm", "asb", "rpivid_asb"; 117 clocks = <&clocks BCM2835_CLOCK_V3D>, 118 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 119 <&clocks BCM2835_CLOCK_H264>, 120 <&clocks BCM2835_CLOCK_ISP>; 121 clock-names = "v3d", "peri_image", "h264", "isp"; 122 system-power-controller; 123 }; 124 125 rng@7e104000 { 126 compatible = "brcm,bcm2711-rng200"; 127 reg = <0x7e104000 0x28>; 128 }; 129 130 uart2: serial@7e201400 { 131 compatible = "arm,pl011", "arm,primecell"; 132 reg = <0x7e201400 0x200>; 133 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&clocks BCM2835_CLOCK_UART>, 135 <&clocks BCM2835_CLOCK_VPU>; 136 clock-names = "uartclk", "apb_pclk"; 137 arm,primecell-periphid = <0x00241011>; 138 status = "disabled"; 139 }; 140 141 uart3: serial@7e201600 { 142 compatible = "arm,pl011", "arm,primecell"; 143 reg = <0x7e201600 0x200>; 144 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&clocks BCM2835_CLOCK_UART>, 146 <&clocks BCM2835_CLOCK_VPU>; 147 clock-names = "uartclk", "apb_pclk"; 148 arm,primecell-periphid = <0x00241011>; 149 status = "disabled"; 150 }; 151 152 uart4: serial@7e201800 { 153 compatible = "arm,pl011", "arm,primecell"; 154 reg = <0x7e201800 0x200>; 155 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&clocks BCM2835_CLOCK_UART>, 157 <&clocks BCM2835_CLOCK_VPU>; 158 clock-names = "uartclk", "apb_pclk"; 159 arm,primecell-periphid = <0x00241011>; 160 status = "disabled"; 161 }; 162 163 uart5: serial@7e201a00 { 164 compatible = "arm,pl011", "arm,primecell"; 165 reg = <0x7e201a00 0x200>; 166 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&clocks BCM2835_CLOCK_UART>, 168 <&clocks BCM2835_CLOCK_VPU>; 169 clock-names = "uartclk", "apb_pclk"; 170 arm,primecell-periphid = <0x00241011>; 171 status = "disabled"; 172 }; 173 174 spi3: spi@7e204600 { 175 compatible = "brcm,bcm2835-spi"; 176 reg = <0x7e204600 0x0200>; 177 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&clocks BCM2835_CLOCK_VPU>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 status = "disabled"; 182 }; 183 184 spi4: spi@7e204800 { 185 compatible = "brcm,bcm2835-spi"; 186 reg = <0x7e204800 0x0200>; 187 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&clocks BCM2835_CLOCK_VPU>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 status = "disabled"; 192 }; 193 194 spi5: spi@7e204a00 { 195 compatible = "brcm,bcm2835-spi"; 196 reg = <0x7e204a00 0x0200>; 197 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&clocks BCM2835_CLOCK_VPU>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 status = "disabled"; 202 }; 203 204 spi6: spi@7e204c00 { 205 compatible = "brcm,bcm2835-spi"; 206 reg = <0x7e204c00 0x0200>; 207 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&clocks BCM2835_CLOCK_VPU>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 status = "disabled"; 212 }; 213 214 i2c3: i2c@7e205600 { 215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 216 reg = <0x7e205600 0x200>; 217 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&clocks BCM2835_CLOCK_VPU>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 status = "disabled"; 222 }; 223 224 i2c4: i2c@7e205800 { 225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 226 reg = <0x7e205800 0x200>; 227 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&clocks BCM2835_CLOCK_VPU>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 status = "disabled"; 232 }; 233 234 i2c5: i2c@7e205a00 { 235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 236 reg = <0x7e205a00 0x200>; 237 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&clocks BCM2835_CLOCK_VPU>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 status = "disabled"; 242 }; 243 244 i2c6: i2c@7e205c00 { 245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 246 reg = <0x7e205c00 0x200>; 247 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clocks BCM2835_CLOCK_VPU>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 status = "disabled"; 252 }; 253 254 pixelvalve0: pixelvalve@7e206000 { 255 compatible = "brcm,bcm2711-pixelvalve0"; 256 reg = <0x7e206000 0x100>; 257 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 258 status = "disabled"; 259 }; 260 261 pixelvalve1: pixelvalve@7e207000 { 262 compatible = "brcm,bcm2711-pixelvalve1"; 263 reg = <0x7e207000 0x100>; 264 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 265 status = "disabled"; 266 }; 267 268 pixelvalve2: pixelvalve@7e20a000 { 269 compatible = "brcm,bcm2711-pixelvalve2"; 270 reg = <0x7e20a000 0x100>; 271 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 272 status = "disabled"; 273 }; 274 275 pwm1: pwm@7e20c800 { 276 compatible = "brcm,bcm2835-pwm"; 277 reg = <0x7e20c800 0x28>; 278 clocks = <&clocks BCM2835_CLOCK_PWM>; 279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 280 assigned-clock-rates = <10000000>; 281 #pwm-cells = <3>; 282 status = "disabled"; 283 }; 284 285 pixelvalve4: pixelvalve@7e216000 { 286 compatible = "brcm,bcm2711-pixelvalve4"; 287 reg = <0x7e216000 0x100>; 288 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 289 status = "disabled"; 290 }; 291 292 hvs: hvs@7e400000 { 293 compatible = "brcm,bcm2711-hvs"; 294 reg = <0x7e400000 0x8000>; 295 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 296 }; 297 298 pixelvalve3: pixelvalve@7ec12000 { 299 compatible = "brcm,bcm2711-pixelvalve3"; 300 reg = <0x7ec12000 0x100>; 301 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 302 status = "disabled"; 303 }; 304 305 vec: vec@7ec13000 { 306 compatible = "brcm,bcm2711-vec"; 307 reg = <0x7ec13000 0x1000>; 308 clocks = <&clocks BCM2835_CLOCK_VEC>; 309 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 310 status = "disabled"; 311 }; 312 313 dvp: clock@7ef00000 { 314 compatible = "brcm,brcm2711-dvp"; 315 reg = <0x7ef00000 0x10>; 316 clocks = <&clk_108MHz>; 317 #clock-cells = <1>; 318 #reset-cells = <1>; 319 }; 320 321 aon_intr: interrupt-controller@7ef00100 { 322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 323 reg = <0x7ef00100 0x30>; 324 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 325 interrupt-controller; 326 #interrupt-cells = <1>; 327 }; 328 329 hdmi0: hdmi@7ef00700 { 330 compatible = "brcm,bcm2711-hdmi0"; 331 reg = <0x7ef00700 0x300>, 332 <0x7ef00300 0x200>, 333 <0x7ef00f00 0x80>, 334 <0x7ef00f80 0x80>, 335 <0x7ef01b00 0x200>, 336 <0x7ef01f00 0x400>, 337 <0x7ef00200 0x80>, 338 <0x7ef04300 0x100>, 339 <0x7ef20000 0x100>; 340 reg-names = "hdmi", 341 "dvp", 342 "phy", 343 "rm", 344 "packet", 345 "metadata", 346 "csc", 347 "cec", 348 "hd"; 349 clock-names = "hdmi", "bvb", "audio", "cec"; 350 resets = <&dvp 0>; 351 interrupt-parent = <&aon_intr>; 352 interrupts = <0>, <1>, <2>, 353 <3>, <4>, <5>; 354 interrupt-names = "cec-tx", "cec-rx", "cec-low", 355 "wakeup", "hpd-connected", "hpd-removed"; 356 ddc = <&ddc0>; 357 dmas = <&dma 10>; 358 dma-names = "audio-rx"; 359 status = "disabled"; 360 }; 361 362 ddc0: i2c@7ef04500 { 363 compatible = "brcm,bcm2711-hdmi-i2c"; 364 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; 365 reg-names = "bsc", "auto-i2c"; 366 clock-frequency = <97500>; 367 status = "disabled"; 368 }; 369 370 hdmi1: hdmi@7ef05700 { 371 compatible = "brcm,bcm2711-hdmi1"; 372 reg = <0x7ef05700 0x300>, 373 <0x7ef05300 0x200>, 374 <0x7ef05f00 0x80>, 375 <0x7ef05f80 0x80>, 376 <0x7ef06b00 0x200>, 377 <0x7ef06f00 0x400>, 378 <0x7ef00280 0x80>, 379 <0x7ef09300 0x100>, 380 <0x7ef20000 0x100>; 381 reg-names = "hdmi", 382 "dvp", 383 "phy", 384 "rm", 385 "packet", 386 "metadata", 387 "csc", 388 "cec", 389 "hd"; 390 ddc = <&ddc1>; 391 clock-names = "hdmi", "bvb", "audio", "cec"; 392 resets = <&dvp 1>; 393 interrupt-parent = <&aon_intr>; 394 interrupts = <8>, <7>, <6>, 395 <9>, <10>, <11>; 396 interrupt-names = "cec-tx", "cec-rx", "cec-low", 397 "wakeup", "hpd-connected", "hpd-removed"; 398 dmas = <&dma 17>; 399 dma-names = "audio-rx"; 400 status = "disabled"; 401 }; 402 403 ddc1: i2c@7ef09500 { 404 compatible = "brcm,bcm2711-hdmi-i2c"; 405 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; 406 reg-names = "bsc", "auto-i2c"; 407 clock-frequency = <97500>; 408 status = "disabled"; 409 }; 410 }; 411 412 /* 413 * emmc2 has different DMA constraints based on SoC revisions. It was 414 * moved into its own bus, so as for RPi4's firmware to update them. 415 * The firmware will find whether the emmc2bus alias is defined, and if 416 * so, it'll edit the dma-ranges property below accordingly. 417 */ 418 emmc2bus: emmc2bus { 419 compatible = "simple-bus"; 420 #address-cells = <2>; 421 #size-cells = <1>; 422 423 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 425 426 emmc2: mmc@7e340000 { 427 compatible = "brcm,bcm2711-emmc2"; 428 reg = <0x0 0x7e340000 0x100>; 429 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 431 status = "disabled"; 432 }; 433 }; 434 435 pmu { 436 compatible = "arm,cortex-a72-pmu"; 437 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 442 }; 443 444 timer { 445 compatible = "arm,armv8-timer"; 446 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 447 IRQ_TYPE_LEVEL_LOW)>, 448 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 449 IRQ_TYPE_LEVEL_LOW)>, 450 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 451 IRQ_TYPE_LEVEL_LOW)>, 452 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 453 IRQ_TYPE_LEVEL_LOW)>; 454 /* This only applies to the ARMv7 stub */ 455 arm,cpu-registers-not-fw-configured; 456 }; 457 458 cpus: cpus { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 462 463 /* Source for d/i-cache-line-size and d/i-cache-sets 464 * https://developer.arm.com/documentation/100095/0003 465 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en 466 * Source for d/i-cache-size 467 * https://www.raspberrypi.com/documentation/computers 468 * /processors.html#bcm2711 469 */ 470 cpu0: cpu@0 { 471 device_type = "cpu"; 472 compatible = "arm,cortex-a72"; 473 reg = <0>; 474 enable-method = "spin-table"; 475 cpu-release-addr = <0x0 0x000000d8>; 476 d-cache-size = <0x8000>; 477 d-cache-line-size = <64>; 478 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 479 i-cache-size = <0xc000>; 480 i-cache-line-size = <64>; 481 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 482 next-level-cache = <&l2>; 483 }; 484 485 cpu1: cpu@1 { 486 device_type = "cpu"; 487 compatible = "arm,cortex-a72"; 488 reg = <1>; 489 enable-method = "spin-table"; 490 cpu-release-addr = <0x0 0x000000e0>; 491 d-cache-size = <0x8000>; 492 d-cache-line-size = <64>; 493 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 494 i-cache-size = <0xc000>; 495 i-cache-line-size = <64>; 496 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 497 next-level-cache = <&l2>; 498 }; 499 500 cpu2: cpu@2 { 501 device_type = "cpu"; 502 compatible = "arm,cortex-a72"; 503 reg = <2>; 504 enable-method = "spin-table"; 505 cpu-release-addr = <0x0 0x000000e8>; 506 d-cache-size = <0x8000>; 507 d-cache-line-size = <64>; 508 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 509 i-cache-size = <0xc000>; 510 i-cache-line-size = <64>; 511 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 512 next-level-cache = <&l2>; 513 }; 514 515 cpu3: cpu@3 { 516 device_type = "cpu"; 517 compatible = "arm,cortex-a72"; 518 reg = <3>; 519 enable-method = "spin-table"; 520 cpu-release-addr = <0x0 0x000000f0>; 521 d-cache-size = <0x8000>; 522 d-cache-line-size = <64>; 523 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 524 i-cache-size = <0xc000>; 525 i-cache-line-size = <64>; 526 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 527 next-level-cache = <&l2>; 528 }; 529 530 /* Source for d/i-cache-line-size and d/i-cache-sets 531 * https://developer.arm.com/documentation/100095/0003 532 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en 533 * Source for d/i-cache-size 534 * https://www.raspberrypi.com/documentation/computers 535 * /processors.html#bcm2711 536 */ 537 l2: l2-cache0 { 538 compatible = "cache"; 539 cache-unified; 540 cache-size = <0x100000>; 541 cache-line-size = <64>; 542 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set 543 cache-level = <2>; 544 }; 545 }; 546 547 scb { 548 compatible = "simple-bus"; 549 #address-cells = <2>; 550 #size-cells = <1>; 551 552 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 553 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 554 555 pcie0: pcie@7d500000 { 556 compatible = "brcm,bcm2711-pcie"; 557 reg = <0x0 0x7d500000 0x9310>; 558 device_type = "pci"; 559 #address-cells = <3>; 560 #interrupt-cells = <1>; 561 #size-cells = <2>; 562 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "pcie", "msi"; 565 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 566 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 567 IRQ_TYPE_LEVEL_HIGH>, 568 <0 0 0 2 &gicv2 GIC_SPI 144 569 IRQ_TYPE_LEVEL_HIGH>, 570 <0 0 0 3 &gicv2 GIC_SPI 145 571 IRQ_TYPE_LEVEL_HIGH>, 572 <0 0 0 4 &gicv2 GIC_SPI 146 573 IRQ_TYPE_LEVEL_HIGH>; 574 msi-controller; 575 msi-parent = <&pcie0>; 576 577 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 578 0x0 0x04000000>; 579 /* 580 * The wrapper around the PCIe block has a bug 581 * preventing it from accessing beyond the first 3GB of 582 * memory. 583 */ 584 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 585 0x0 0xc0000000>; 586 brcm,enable-ssc; 587 }; 588 589 genet: ethernet@7d580000 { 590 compatible = "brcm,bcm2711-genet-v5"; 591 reg = <0x0 0x7d580000 0x10000>; 592 #address-cells = <0x1>; 593 #size-cells = <0x1>; 594 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 596 status = "disabled"; 597 598 genet_mdio: mdio@e14 { 599 compatible = "brcm,genet-mdio-v5"; 600 reg = <0xe14 0x8>; 601 reg-names = "mdio"; 602 #address-cells = <0x1>; 603 #size-cells = <0x0>; 604 }; 605 }; 606 607 xhci: usb@7e9c0000 { 608 compatible = "brcm,bcm2711-xhci", "brcm,xhci-brcm-v2"; 609 reg = <0x0 0x7e9c0000 0x100000>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 613 /* DWC2 and this IP block share the same USB PHY, 614 * enabling both at the same time results in lockups. 615 * So keep this node disabled and let the bootloader 616 * decide which interface should be enabled. 617 */ 618 status = "disabled"; 619 }; 620 621 v3d: gpu@7ec00000 { 622 compatible = "brcm,2711-v3d"; 623 reg = <0x0 0x7ec00000 0x4000>, 624 <0x0 0x7ec04000 0x4000>; 625 reg-names = "hub", "core0"; 626 627 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; 628 resets = <&pm BCM2835_RESET_V3D>; 629 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 630 }; 631 }; 632}; 633 634&clk_osc { 635 clock-frequency = <54000000>; 636}; 637 638&clocks { 639 compatible = "brcm,bcm2711-cprman"; 640}; 641 642&cpu_thermal { 643 coefficients = <(-487) 410040>; 644 thermal-sensors = <&thermal>; 645}; 646 647&dsi0 { 648 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 649}; 650 651&dsi1 { 652 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 653 compatible = "brcm,bcm2711-dsi1"; 654}; 655 656&gpio { 657 compatible = "brcm,bcm2711-gpio"; 658 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 662 663 gpio-ranges = <&gpio 0 0 58>; 664 665 gpclk0_gpio49: gpclk0-gpio49 { 666 pin-gpclk { 667 pins = "gpio49"; 668 function = "alt1"; 669 bias-disable; 670 }; 671 }; 672 gpclk1_gpio50: gpclk1-gpio50 { 673 pin-gpclk { 674 pins = "gpio50"; 675 function = "alt1"; 676 bias-disable; 677 }; 678 }; 679 gpclk2_gpio51: gpclk2-gpio51 { 680 pin-gpclk { 681 pins = "gpio51"; 682 function = "alt1"; 683 bias-disable; 684 }; 685 }; 686 687 i2c0_gpio46: i2c0-gpio46 { 688 pin-sda { 689 function = "alt0"; 690 pins = "gpio46"; 691 bias-pull-up; 692 }; 693 pin-scl { 694 function = "alt0"; 695 pins = "gpio47"; 696 bias-disable; 697 }; 698 }; 699 i2c1_gpio46: i2c1-gpio46 { 700 pin-sda { 701 function = "alt1"; 702 pins = "gpio46"; 703 bias-pull-up; 704 }; 705 pin-scl { 706 function = "alt1"; 707 pins = "gpio47"; 708 bias-disable; 709 }; 710 }; 711 i2c3_gpio2: i2c3-gpio2 { 712 pin-sda { 713 function = "alt5"; 714 pins = "gpio2"; 715 bias-pull-up; 716 }; 717 pin-scl { 718 function = "alt5"; 719 pins = "gpio3"; 720 bias-disable; 721 }; 722 }; 723 i2c3_gpio4: i2c3-gpio4 { 724 pin-sda { 725 function = "alt5"; 726 pins = "gpio4"; 727 bias-pull-up; 728 }; 729 pin-scl { 730 function = "alt5"; 731 pins = "gpio5"; 732 bias-disable; 733 }; 734 }; 735 i2c4_gpio6: i2c4-gpio6 { 736 pin-sda { 737 function = "alt5"; 738 pins = "gpio6"; 739 bias-pull-up; 740 }; 741 pin-scl { 742 function = "alt5"; 743 pins = "gpio7"; 744 bias-disable; 745 }; 746 }; 747 i2c4_gpio8: i2c4-gpio8 { 748 pin-sda { 749 function = "alt5"; 750 pins = "gpio8"; 751 bias-pull-up; 752 }; 753 pin-scl { 754 function = "alt5"; 755 pins = "gpio9"; 756 bias-disable; 757 }; 758 }; 759 i2c5_gpio10: i2c5-gpio10 { 760 pin-sda { 761 function = "alt5"; 762 pins = "gpio10"; 763 bias-pull-up; 764 }; 765 pin-scl { 766 function = "alt5"; 767 pins = "gpio11"; 768 bias-disable; 769 }; 770 }; 771 i2c5_gpio12: i2c5-gpio12 { 772 pin-sda { 773 function = "alt5"; 774 pins = "gpio12"; 775 bias-pull-up; 776 }; 777 pin-scl { 778 function = "alt5"; 779 pins = "gpio13"; 780 bias-disable; 781 }; 782 }; 783 i2c6_gpio0: i2c6-gpio0 { 784 pin-sda { 785 function = "alt5"; 786 pins = "gpio0"; 787 bias-pull-up; 788 }; 789 pin-scl { 790 function = "alt5"; 791 pins = "gpio1"; 792 bias-disable; 793 }; 794 }; 795 i2c6_gpio22: i2c6-gpio22 { 796 pin-sda { 797 function = "alt5"; 798 pins = "gpio22"; 799 bias-pull-up; 800 }; 801 pin-scl { 802 function = "alt5"; 803 pins = "gpio23"; 804 bias-disable; 805 }; 806 }; 807 i2c_slave_gpio8: i2c-slave-gpio8 { 808 pins-i2c-slave { 809 pins = "gpio8", 810 "gpio9", 811 "gpio10", 812 "gpio11"; 813 function = "alt3"; 814 }; 815 }; 816 817 jtag_gpio48: jtag-gpio48 { 818 pins-jtag { 819 pins = "gpio48", 820 "gpio49", 821 "gpio50", 822 "gpio51", 823 "gpio52", 824 "gpio53"; 825 function = "alt4"; 826 }; 827 }; 828 829 mii_gpio28: mii-gpio28 { 830 pins-mii { 831 pins = "gpio28", 832 "gpio29", 833 "gpio30", 834 "gpio31"; 835 function = "alt4"; 836 }; 837 }; 838 mii_gpio36: mii-gpio36 { 839 pins-mii { 840 pins = "gpio36", 841 "gpio37", 842 "gpio38", 843 "gpio39"; 844 function = "alt5"; 845 }; 846 }; 847 848 pcm_gpio50: pcm-gpio50 { 849 pins-pcm { 850 pins = "gpio50", 851 "gpio51", 852 "gpio52", 853 "gpio53"; 854 function = "alt2"; 855 }; 856 }; 857 858 pwm0_0_gpio12: pwm0-0-gpio12 { 859 pin-pwm { 860 pins = "gpio12"; 861 function = "alt0"; 862 bias-disable; 863 }; 864 }; 865 pwm0_0_gpio18: pwm0-0-gpio18 { 866 pin-pwm { 867 pins = "gpio18"; 868 function = "alt5"; 869 bias-disable; 870 }; 871 }; 872 pwm1_0_gpio40: pwm1-0-gpio40 { 873 pin-pwm { 874 pins = "gpio40"; 875 function = "alt0"; 876 bias-disable; 877 }; 878 }; 879 pwm0_1_gpio13: pwm0-1-gpio13 { 880 pin-pwm { 881 pins = "gpio13"; 882 function = "alt0"; 883 bias-disable; 884 }; 885 }; 886 pwm0_1_gpio19: pwm0-1-gpio19 { 887 pin-pwm { 888 pins = "gpio19"; 889 function = "alt5"; 890 bias-disable; 891 }; 892 }; 893 pwm1_1_gpio41: pwm1-1-gpio41 { 894 pin-pwm { 895 pins = "gpio41"; 896 function = "alt0"; 897 bias-disable; 898 }; 899 }; 900 pwm0_1_gpio45: pwm0-1-gpio45 { 901 pin-pwm { 902 pins = "gpio45"; 903 function = "alt0"; 904 bias-disable; 905 }; 906 }; 907 pwm0_0_gpio52: pwm0-0-gpio52 { 908 pin-pwm { 909 pins = "gpio52"; 910 function = "alt1"; 911 bias-disable; 912 }; 913 }; 914 pwm0_1_gpio53: pwm0-1-gpio53 { 915 pin-pwm { 916 pins = "gpio53"; 917 function = "alt1"; 918 bias-disable; 919 }; 920 }; 921 922 rgmii_gpio35: rgmii-gpio35 { 923 pin-start-stop { 924 pins = "gpio35"; 925 function = "alt4"; 926 }; 927 pin-rx-ok { 928 pins = "gpio36"; 929 function = "alt4"; 930 }; 931 }; 932 rgmii_irq_gpio34: rgmii-irq-gpio34 { 933 pin-irq { 934 pins = "gpio34"; 935 function = "alt5"; 936 }; 937 }; 938 rgmii_irq_gpio39: rgmii-irq-gpio39 { 939 pin-irq { 940 pins = "gpio39"; 941 function = "alt4"; 942 }; 943 }; 944 rgmii_mdio_gpio28: rgmii-mdio-gpio28 { 945 pins-mdio { 946 pins = "gpio28", 947 "gpio29"; 948 function = "alt5"; 949 }; 950 }; 951 rgmii_mdio_gpio37: rgmii-mdio-gpio37 { 952 pins-mdio { 953 pins = "gpio37", 954 "gpio38"; 955 function = "alt4"; 956 }; 957 }; 958 959 spi0_gpio46: spi0-gpio46 { 960 pins-spi { 961 pins = "gpio46", 962 "gpio47", 963 "gpio48", 964 "gpio49"; 965 function = "alt2"; 966 }; 967 }; 968 spi2_gpio46: spi2-gpio46 { 969 pins-spi { 970 pins = "gpio46", 971 "gpio47", 972 "gpio48", 973 "gpio49", 974 "gpio50"; 975 function = "alt5"; 976 }; 977 }; 978 spi3_gpio0: spi3-gpio0 { 979 pins-spi { 980 pins = "gpio0", 981 "gpio1", 982 "gpio2", 983 "gpio3"; 984 function = "alt3"; 985 }; 986 }; 987 spi4_gpio4: spi4-gpio4 { 988 pins-spi { 989 pins = "gpio4", 990 "gpio5", 991 "gpio6", 992 "gpio7"; 993 function = "alt3"; 994 }; 995 }; 996 spi5_gpio12: spi5-gpio12 { 997 pins-spi { 998 pins = "gpio12", 999 "gpio13", 1000 "gpio14", 1001 "gpio15"; 1002 function = "alt3"; 1003 }; 1004 }; 1005 spi6_gpio18: spi6-gpio18 { 1006 pins-spi { 1007 pins = "gpio18", 1008 "gpio19", 1009 "gpio20", 1010 "gpio21"; 1011 function = "alt3"; 1012 }; 1013 }; 1014 1015 uart2_gpio0: uart2-gpio0 { 1016 pin-tx { 1017 pins = "gpio0"; 1018 function = "alt4"; 1019 bias-disable; 1020 }; 1021 pin-rx { 1022 pins = "gpio1"; 1023 function = "alt4"; 1024 bias-pull-up; 1025 }; 1026 }; 1027 uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 { 1028 pin-cts { 1029 pins = "gpio2"; 1030 function = "alt4"; 1031 bias-pull-up; 1032 }; 1033 pin-rts { 1034 pins = "gpio3"; 1035 function = "alt4"; 1036 bias-disable; 1037 }; 1038 }; 1039 uart3_gpio4: uart3-gpio4 { 1040 pin-tx { 1041 pins = "gpio4"; 1042 function = "alt4"; 1043 bias-disable; 1044 }; 1045 pin-rx { 1046 pins = "gpio5"; 1047 function = "alt4"; 1048 bias-pull-up; 1049 }; 1050 }; 1051 uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 { 1052 pin-cts { 1053 pins = "gpio6"; 1054 function = "alt4"; 1055 bias-pull-up; 1056 }; 1057 pin-rts { 1058 pins = "gpio7"; 1059 function = "alt4"; 1060 bias-disable; 1061 }; 1062 }; 1063 uart4_gpio8: uart4-gpio8 { 1064 pin-tx { 1065 pins = "gpio8"; 1066 function = "alt4"; 1067 bias-disable; 1068 }; 1069 pin-rx { 1070 pins = "gpio9"; 1071 function = "alt4"; 1072 bias-pull-up; 1073 }; 1074 }; 1075 uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 { 1076 pin-cts { 1077 pins = "gpio10"; 1078 function = "alt4"; 1079 bias-pull-up; 1080 }; 1081 pin-rts { 1082 pins = "gpio11"; 1083 function = "alt4"; 1084 bias-disable; 1085 }; 1086 }; 1087 uart5_gpio12: uart5-gpio12 { 1088 pin-tx { 1089 pins = "gpio12"; 1090 function = "alt4"; 1091 bias-disable; 1092 }; 1093 pin-rx { 1094 pins = "gpio13"; 1095 function = "alt4"; 1096 bias-pull-up; 1097 }; 1098 }; 1099 uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 { 1100 pin-cts { 1101 pins = "gpio14"; 1102 function = "alt4"; 1103 bias-pull-up; 1104 }; 1105 pin-rts { 1106 pins = "gpio15"; 1107 function = "alt4"; 1108 bias-disable; 1109 }; 1110 }; 1111}; 1112 1113&rmem { 1114 #address-cells = <2>; 1115}; 1116 1117&csi0 { 1118 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1119}; 1120 1121&csi1 { 1122 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1123}; 1124 1125&cma { 1126 /* 1127 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 1128 * that's not good enough for the BCM2711 as some devices can 1129 * only address the lower 1G of memory (ZONE_DMA). 1130 */ 1131 alloc-ranges = <0x0 0x00000000 0x40000000>; 1132}; 1133 1134&i2c0 { 1135 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1136 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1137}; 1138 1139&i2c1 { 1140 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1141 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1142}; 1143 1144&mailbox { 1145 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1146}; 1147 1148&sdhci { 1149 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1150}; 1151 1152&sdhost { 1153 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1154}; 1155 1156&spi { 1157 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1158}; 1159 1160&spi1 { 1161 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1162}; 1163 1164&spi2 { 1165 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1166}; 1167 1168&system_timer { 1169 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1173}; 1174 1175&txp { 1176 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1177}; 1178 1179&uart0 { 1180 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1181}; 1182 1183&uart1 { 1184 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1185}; 1186 1187&usb { 1188 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1189}; 1190 1191&vec { 1192 compatible = "brcm,bcm2711-vec"; 1193 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1194}; 1195