1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _athub_4_1_0_SH_MASK_HEADER 24 #define _athub_4_1_0_SH_MASK_HEADER 25 26 27 // addressBlock: athub_xpbdec 28 //XPB_RTR_SRC_APRTR0 29 #define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 30 #define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 31 //XPB_RTR_SRC_APRTR1 32 #define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 33 #define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 34 //XPB_RTR_SRC_APRTR2 35 #define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 36 #define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 37 //XPB_RTR_SRC_APRTR3 38 #define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 39 #define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 40 //XPB_RTR_SRC_APRTR4 41 #define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 42 #define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL 43 //XPB_RTR_SRC_APRTR5 44 #define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 45 #define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL 46 //XPB_RTR_SRC_APRTR6 47 #define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 48 #define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL 49 //XPB_RTR_SRC_APRTR7 50 #define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 51 #define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL 52 //XPB_RTR_SRC_APRTR8 53 #define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 54 #define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL 55 //XPB_RTR_SRC_APRTR9 56 #define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 57 #define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL 58 //XPB_RTR_SRC_APRTR10 59 #define XPB_RTR_SRC_APRTR10__BASE_ADDR__SHIFT 0x0 60 #define XPB_RTR_SRC_APRTR10__BASE_ADDR_MASK 0x7FFFFFFFL 61 //XPB_RTR_SRC_APRTR11 62 #define XPB_RTR_SRC_APRTR11__BASE_ADDR__SHIFT 0x0 63 #define XPB_RTR_SRC_APRTR11__BASE_ADDR_MASK 0x7FFFFFFFL 64 //XPB_RTR_SRC_APRTR12 65 #define XPB_RTR_SRC_APRTR12__BASE_ADDR__SHIFT 0x0 66 #define XPB_RTR_SRC_APRTR12__BASE_ADDR_MASK 0x7FFFFFFFL 67 //XPB_RTR_SRC_APRTR13 68 #define XPB_RTR_SRC_APRTR13__BASE_ADDR__SHIFT 0x0 69 #define XPB_RTR_SRC_APRTR13__BASE_ADDR_MASK 0x7FFFFFFFL 70 //XPB_RTR_DEST_MAP0 71 #define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 72 #define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 73 #define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 74 #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 75 #define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 76 #define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 77 #define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 78 #define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 79 #define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 80 #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 81 #define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 82 #define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 83 //XPB_RTR_DEST_MAP1 84 #define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 85 #define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 86 #define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 87 #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 88 #define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 89 #define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 90 #define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 91 #define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 92 #define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 93 #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 94 #define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 95 #define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 96 //XPB_RTR_DEST_MAP2 97 #define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 98 #define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 99 #define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 100 #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 101 #define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 102 #define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 103 #define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 104 #define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 105 #define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 106 #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 107 #define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 108 #define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 109 //XPB_RTR_DEST_MAP3 110 #define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 111 #define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 112 #define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 113 #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 114 #define XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 115 #define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 116 #define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 117 #define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 118 #define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 119 #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 120 #define XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 121 #define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 122 //XPB_RTR_DEST_MAP4 123 #define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 124 #define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 125 #define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 126 #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 127 #define XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 128 #define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 129 #define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 130 #define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL 131 #define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L 132 #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 133 #define XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L 134 #define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L 135 //XPB_RTR_DEST_MAP5 136 #define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 137 #define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 138 #define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 139 #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 140 #define XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 141 #define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 142 #define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 143 #define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL 144 #define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L 145 #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 146 #define XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L 147 #define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L 148 //XPB_RTR_DEST_MAP6 149 #define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 150 #define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 151 #define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 152 #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 153 #define XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 154 #define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 155 #define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 156 #define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL 157 #define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L 158 #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 159 #define XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L 160 #define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L 161 //XPB_RTR_DEST_MAP7 162 #define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 163 #define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 164 #define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 165 #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 166 #define XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 167 #define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 168 #define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 169 #define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL 170 #define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L 171 #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 172 #define XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L 173 #define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L 174 //XPB_RTR_DEST_MAP8 175 #define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 176 #define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 177 #define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 178 #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 179 #define XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 180 #define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 181 #define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 182 #define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL 183 #define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L 184 #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 185 #define XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L 186 #define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L 187 //XPB_RTR_DEST_MAP9 188 #define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 189 #define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 190 #define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 191 #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 192 #define XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 193 #define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 194 #define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 195 #define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL 196 #define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L 197 #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 198 #define XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L 199 #define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L 200 //XPB_RTR_DEST_MAP10 201 #define XPB_RTR_DEST_MAP10__NMR__SHIFT 0x0 202 #define XPB_RTR_DEST_MAP10__DEST_OFFSET__SHIFT 0x1 203 #define XPB_RTR_DEST_MAP10__DEST_SEL__SHIFT 0x14 204 #define XPB_RTR_DEST_MAP10__DEST_SEL_RPB__SHIFT 0x18 205 #define XPB_RTR_DEST_MAP10__SIDE_OK__SHIFT 0x19 206 #define XPB_RTR_DEST_MAP10__APRTR_SIZE__SHIFT 0x1a 207 #define XPB_RTR_DEST_MAP10__NMR_MASK 0x00000001L 208 #define XPB_RTR_DEST_MAP10__DEST_OFFSET_MASK 0x000FFFFEL 209 #define XPB_RTR_DEST_MAP10__DEST_SEL_MASK 0x00F00000L 210 #define XPB_RTR_DEST_MAP10__DEST_SEL_RPB_MASK 0x01000000L 211 #define XPB_RTR_DEST_MAP10__SIDE_OK_MASK 0x02000000L 212 #define XPB_RTR_DEST_MAP10__APRTR_SIZE_MASK 0x7C000000L 213 //XPB_RTR_DEST_MAP11 214 #define XPB_RTR_DEST_MAP11__NMR__SHIFT 0x0 215 #define XPB_RTR_DEST_MAP11__DEST_OFFSET__SHIFT 0x1 216 #define XPB_RTR_DEST_MAP11__DEST_SEL__SHIFT 0x14 217 #define XPB_RTR_DEST_MAP11__DEST_SEL_RPB__SHIFT 0x18 218 #define XPB_RTR_DEST_MAP11__SIDE_OK__SHIFT 0x19 219 #define XPB_RTR_DEST_MAP11__APRTR_SIZE__SHIFT 0x1a 220 #define XPB_RTR_DEST_MAP11__NMR_MASK 0x00000001L 221 #define XPB_RTR_DEST_MAP11__DEST_OFFSET_MASK 0x000FFFFEL 222 #define XPB_RTR_DEST_MAP11__DEST_SEL_MASK 0x00F00000L 223 #define XPB_RTR_DEST_MAP11__DEST_SEL_RPB_MASK 0x01000000L 224 #define XPB_RTR_DEST_MAP11__SIDE_OK_MASK 0x02000000L 225 #define XPB_RTR_DEST_MAP11__APRTR_SIZE_MASK 0x7C000000L 226 //XPB_RTR_DEST_MAP12 227 #define XPB_RTR_DEST_MAP12__NMR__SHIFT 0x0 228 #define XPB_RTR_DEST_MAP12__DEST_OFFSET__SHIFT 0x1 229 #define XPB_RTR_DEST_MAP12__DEST_SEL__SHIFT 0x14 230 #define XPB_RTR_DEST_MAP12__DEST_SEL_RPB__SHIFT 0x18 231 #define XPB_RTR_DEST_MAP12__SIDE_OK__SHIFT 0x19 232 #define XPB_RTR_DEST_MAP12__APRTR_SIZE__SHIFT 0x1a 233 #define XPB_RTR_DEST_MAP12__NMR_MASK 0x00000001L 234 #define XPB_RTR_DEST_MAP12__DEST_OFFSET_MASK 0x000FFFFEL 235 #define XPB_RTR_DEST_MAP12__DEST_SEL_MASK 0x00F00000L 236 #define XPB_RTR_DEST_MAP12__DEST_SEL_RPB_MASK 0x01000000L 237 #define XPB_RTR_DEST_MAP12__SIDE_OK_MASK 0x02000000L 238 #define XPB_RTR_DEST_MAP12__APRTR_SIZE_MASK 0x7C000000L 239 //XPB_RTR_DEST_MAP13 240 #define XPB_RTR_DEST_MAP13__NMR__SHIFT 0x0 241 #define XPB_RTR_DEST_MAP13__DEST_OFFSET__SHIFT 0x1 242 #define XPB_RTR_DEST_MAP13__DEST_SEL__SHIFT 0x14 243 #define XPB_RTR_DEST_MAP13__DEST_SEL_RPB__SHIFT 0x18 244 #define XPB_RTR_DEST_MAP13__SIDE_OK__SHIFT 0x19 245 #define XPB_RTR_DEST_MAP13__APRTR_SIZE__SHIFT 0x1a 246 #define XPB_RTR_DEST_MAP13__NMR_MASK 0x00000001L 247 #define XPB_RTR_DEST_MAP13__DEST_OFFSET_MASK 0x000FFFFEL 248 #define XPB_RTR_DEST_MAP13__DEST_SEL_MASK 0x00F00000L 249 #define XPB_RTR_DEST_MAP13__DEST_SEL_RPB_MASK 0x01000000L 250 #define XPB_RTR_DEST_MAP13__SIDE_OK_MASK 0x02000000L 251 #define XPB_RTR_DEST_MAP13__APRTR_SIZE_MASK 0x7C000000L 252 //XPB_CLG_CFG0 253 #define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 254 #define XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 255 #define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 256 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 257 #define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe 258 #define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL 259 #define XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L 260 #define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 261 #define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L 262 #define XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003C000L 263 //XPB_CLG_CFG1 264 #define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 265 #define XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 266 #define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 267 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 268 #define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe 269 #define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL 270 #define XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L 271 #define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 272 #define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L 273 #define XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003C000L 274 //XPB_CLG_CFG2 275 #define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 276 #define XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 277 #define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 278 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 279 #define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe 280 #define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL 281 #define XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L 282 #define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 283 #define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L 284 #define XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003C000L 285 //XPB_CLG_CFG3 286 #define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 287 #define XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 288 #define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 289 #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 290 #define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe 291 #define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL 292 #define XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L 293 #define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 294 #define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L 295 #define XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003C000L 296 //XPB_CLG_CFG4 297 #define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 298 #define XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 299 #define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 300 #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 301 #define XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe 302 #define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL 303 #define XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L 304 #define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 305 #define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L 306 #define XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003C000L 307 //XPB_CLG_CFG5 308 #define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 309 #define XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 310 #define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 311 #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 312 #define XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe 313 #define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL 314 #define XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L 315 #define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 316 #define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L 317 #define XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003C000L 318 //XPB_CLG_CFG6 319 #define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 320 #define XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 321 #define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 322 #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 323 #define XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe 324 #define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL 325 #define XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L 326 #define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 327 #define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L 328 #define XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003C000L 329 //XPB_CLG_CFG7 330 #define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 331 #define XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 332 #define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 333 #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 334 #define XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe 335 #define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL 336 #define XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L 337 #define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 338 #define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L 339 #define XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003C000L 340 //XPB_CLG_EXTRA0 341 #define XPB_CLG_EXTRA0__CMP0_HIGH__SHIFT 0x0 342 #define XPB_CLG_EXTRA0__CMP0_LOW__SHIFT 0x8 343 #define XPB_CLG_EXTRA0__VLD0__SHIFT 0xd 344 #define XPB_CLG_EXTRA0__CLG0_NUM__SHIFT 0xe 345 #define XPB_CLG_EXTRA0__CMP0_HIGH_MASK 0x000000FFL 346 #define XPB_CLG_EXTRA0__CMP0_LOW_MASK 0x00001F00L 347 #define XPB_CLG_EXTRA0__VLD0_MASK 0x00002000L 348 #define XPB_CLG_EXTRA0__CLG0_NUM_MASK 0x0001C000L 349 //XPB_CLG_EXTRA1 350 #define XPB_CLG_EXTRA1__CMP1_HIGH__SHIFT 0x0 351 #define XPB_CLG_EXTRA1__CMP1_LOW__SHIFT 0x8 352 #define XPB_CLG_EXTRA1__VLD1__SHIFT 0xd 353 #define XPB_CLG_EXTRA1__CLG1_NUM__SHIFT 0xe 354 #define XPB_CLG_EXTRA1__CMP1_HIGH_MASK 0x000000FFL 355 #define XPB_CLG_EXTRA1__CMP1_LOW_MASK 0x00001F00L 356 #define XPB_CLG_EXTRA1__VLD1_MASK 0x00002000L 357 #define XPB_CLG_EXTRA1__CLG1_NUM_MASK 0x0001C000L 358 //XPB_CLG_EXTRA_MSK 359 #define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 360 #define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x8 361 #define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xd 362 #define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x15 363 #define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x000000FFL 364 #define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x00001F00L 365 #define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x001FE000L 366 #define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x03E00000L 367 //XPB_LB_ADDR 368 #define XPB_LB_ADDR__CMP0__SHIFT 0x0 369 #define XPB_LB_ADDR__MASK0__SHIFT 0xa 370 #define XPB_LB_ADDR__CMP1__SHIFT 0x14 371 #define XPB_LB_ADDR__MASK1__SHIFT 0x1a 372 #define XPB_LB_ADDR__CMP0_MASK 0x000003FFL 373 #define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L 374 #define XPB_LB_ADDR__CMP1_MASK 0x03F00000L 375 #define XPB_LB_ADDR__MASK1_MASK 0xFC000000L 376 //XPB_HST_CFG 377 #define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 378 #define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L 379 //XPB_P2P_BAR_CFG 380 #define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 381 #define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 382 #define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 383 #define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 384 #define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 385 #define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 386 #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 387 #define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 388 #define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 389 #define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL 390 #define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 391 #define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 392 #define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 393 #define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 394 #define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 395 #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 396 #define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 397 #define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 398 //XPB_P2P_BAR0 399 #define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 400 #define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 401 #define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 402 #define XPB_P2P_BAR0__VALID__SHIFT 0xc 403 #define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 404 #define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 405 #define XPB_P2P_BAR0__RESERVE__SHIFT 0xf 406 #define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 407 #define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL 408 #define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L 409 #define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L 410 #define XPB_P2P_BAR0__VALID_MASK 0x00001000L 411 #define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 412 #define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 413 #define XPB_P2P_BAR0__RESERVE_MASK 0x00008000L 414 #define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L 415 //XPB_P2P_BAR1 416 #define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 417 #define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 418 #define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 419 #define XPB_P2P_BAR1__VALID__SHIFT 0xc 420 #define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 421 #define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 422 #define XPB_P2P_BAR1__RESERVE__SHIFT 0xf 423 #define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 424 #define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL 425 #define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L 426 #define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L 427 #define XPB_P2P_BAR1__VALID_MASK 0x00001000L 428 #define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 429 #define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 430 #define XPB_P2P_BAR1__RESERVE_MASK 0x00008000L 431 #define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L 432 //XPB_P2P_BAR2 433 #define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 434 #define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 435 #define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 436 #define XPB_P2P_BAR2__VALID__SHIFT 0xc 437 #define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 438 #define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 439 #define XPB_P2P_BAR2__RESERVE__SHIFT 0xf 440 #define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 441 #define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL 442 #define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L 443 #define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L 444 #define XPB_P2P_BAR2__VALID_MASK 0x00001000L 445 #define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 446 #define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 447 #define XPB_P2P_BAR2__RESERVE_MASK 0x00008000L 448 #define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L 449 //XPB_P2P_BAR3 450 #define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 451 #define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 452 #define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 453 #define XPB_P2P_BAR3__VALID__SHIFT 0xc 454 #define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 455 #define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 456 #define XPB_P2P_BAR3__RESERVE__SHIFT 0xf 457 #define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 458 #define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL 459 #define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L 460 #define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L 461 #define XPB_P2P_BAR3__VALID_MASK 0x00001000L 462 #define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 463 #define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 464 #define XPB_P2P_BAR3__RESERVE_MASK 0x00008000L 465 #define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L 466 //XPB_P2P_BAR4 467 #define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 468 #define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 469 #define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 470 #define XPB_P2P_BAR4__VALID__SHIFT 0xc 471 #define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 472 #define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 473 #define XPB_P2P_BAR4__RESERVE__SHIFT 0xf 474 #define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 475 #define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL 476 #define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L 477 #define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L 478 #define XPB_P2P_BAR4__VALID_MASK 0x00001000L 479 #define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 480 #define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 481 #define XPB_P2P_BAR4__RESERVE_MASK 0x00008000L 482 #define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L 483 //XPB_P2P_BAR5 484 #define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 485 #define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 486 #define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 487 #define XPB_P2P_BAR5__VALID__SHIFT 0xc 488 #define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 489 #define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 490 #define XPB_P2P_BAR5__RESERVE__SHIFT 0xf 491 #define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 492 #define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL 493 #define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L 494 #define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L 495 #define XPB_P2P_BAR5__VALID_MASK 0x00001000L 496 #define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 497 #define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 498 #define XPB_P2P_BAR5__RESERVE_MASK 0x00008000L 499 #define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L 500 //XPB_P2P_BAR6 501 #define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 502 #define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 503 #define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 504 #define XPB_P2P_BAR6__VALID__SHIFT 0xc 505 #define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 506 #define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 507 #define XPB_P2P_BAR6__RESERVE__SHIFT 0xf 508 #define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 509 #define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL 510 #define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L 511 #define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L 512 #define XPB_P2P_BAR6__VALID_MASK 0x00001000L 513 #define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 514 #define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 515 #define XPB_P2P_BAR6__RESERVE_MASK 0x00008000L 516 #define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L 517 //XPB_P2P_BAR7 518 #define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 519 #define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 520 #define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 521 #define XPB_P2P_BAR7__VALID__SHIFT 0xc 522 #define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 523 #define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 524 #define XPB_P2P_BAR7__RESERVE__SHIFT 0xf 525 #define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 526 #define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL 527 #define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L 528 #define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L 529 #define XPB_P2P_BAR7__VALID_MASK 0x00001000L 530 #define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 531 #define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 532 #define XPB_P2P_BAR7__RESERVE_MASK 0x00008000L 533 #define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L 534 //XPB_P2P_BAR_SETUP 535 #define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 536 #define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 537 #define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 538 #define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 539 #define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 540 #define XPB_P2P_BAR_SETUP__RESERVE__SHIFT 0xf 541 #define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 542 #define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL 543 #define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L 544 #define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 545 #define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 546 #define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 547 #define XPB_P2P_BAR_SETUP__RESERVE_MASK 0x00008000L 548 #define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L 549 //XPB_P2P_BAR_DELTA_ABOVE 550 #define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 551 #define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 552 #define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL 553 #define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L 554 //XPB_P2P_BAR_DELTA_BELOW 555 #define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 556 #define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 557 #define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL 558 #define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L 559 //XPB_PEER_SYS_BAR0 560 #define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 561 #define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 562 #define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 563 #define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 564 //XPB_PEER_SYS_BAR1 565 #define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 566 #define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 567 #define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 568 #define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 569 //XPB_PEER_SYS_BAR2 570 #define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 571 #define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 572 #define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 573 #define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 574 //XPB_PEER_SYS_BAR3 575 #define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 576 #define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 577 #define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 578 #define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 579 //XPB_PEER_SYS_BAR4 580 #define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 581 #define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 582 #define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 583 #define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL 584 //XPB_PEER_SYS_BAR5 585 #define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 586 #define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 587 #define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 588 #define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL 589 //XPB_PEER_SYS_BAR6 590 #define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 591 #define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 592 #define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 593 #define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL 594 //XPB_PEER_SYS_BAR7 595 #define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 596 #define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 597 #define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 598 #define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL 599 //XPB_PEER_SYS_BAR8 600 #define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 601 #define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 602 #define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 603 #define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL 604 //XPB_PEER_SYS_BAR9 605 #define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 606 #define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 607 #define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 608 #define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL 609 //XPB_PEER_SYS_BAR10 610 #define XPB_PEER_SYS_BAR10__VALID__SHIFT 0x0 611 #define XPB_PEER_SYS_BAR10__ADDR__SHIFT 0x1 612 #define XPB_PEER_SYS_BAR10__VALID_MASK 0x00000001L 613 #define XPB_PEER_SYS_BAR10__ADDR_MASK 0xFFFFFFFEL 614 //XPB_PEER_SYS_BAR11 615 #define XPB_PEER_SYS_BAR11__VALID__SHIFT 0x0 616 #define XPB_PEER_SYS_BAR11__ADDR__SHIFT 0x1 617 #define XPB_PEER_SYS_BAR11__VALID_MASK 0x00000001L 618 #define XPB_PEER_SYS_BAR11__ADDR_MASK 0xFFFFFFFEL 619 //XPB_PEER_SYS_BAR12 620 #define XPB_PEER_SYS_BAR12__VALID__SHIFT 0x0 621 #define XPB_PEER_SYS_BAR12__ADDR__SHIFT 0x1 622 #define XPB_PEER_SYS_BAR12__VALID_MASK 0x00000001L 623 #define XPB_PEER_SYS_BAR12__ADDR_MASK 0xFFFFFFFEL 624 //XPB_PEER_SYS_BAR13 625 #define XPB_PEER_SYS_BAR13__VALID__SHIFT 0x0 626 #define XPB_PEER_SYS_BAR13__ADDR__SHIFT 0x1 627 #define XPB_PEER_SYS_BAR13__VALID_MASK 0x00000001L 628 #define XPB_PEER_SYS_BAR13__ADDR_MASK 0xFFFFFFFEL 629 //XPB_CLK_GAT 630 #define XPB_CLK_GAT__ONDLY__SHIFT 0x0 631 #define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 632 #define XPB_CLK_GAT__RDYDLY__SHIFT 0xc 633 #define XPB_CLK_GAT__ENABLE__SHIFT 0x12 634 #define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 635 #define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL 636 #define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L 637 #define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L 638 #define XPB_CLK_GAT__ENABLE_MASK 0x00040000L 639 #define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 640 //XPB_INTF_CFG 641 #define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 642 #define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 643 #define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 644 #define XPB_INTF_CFG__P2P_WR_CHAIN_BREAK__SHIFT 0x17 645 #define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 646 #define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 647 #define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 648 #define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA__SHIFT 0x1f 649 #define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL 650 #define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L 651 #define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L 652 #define XPB_INTF_CFG__P2P_WR_CHAIN_BREAK_MASK 0x00800000L 653 #define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 654 #define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 655 #define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 656 #define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA_MASK 0x80000000L 657 //XPB_INTF_STS 658 #define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 659 #define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 660 #define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 661 #define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 662 #define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 663 #define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 664 #define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 665 #define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL 666 #define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L 667 #define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 668 #define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 669 #define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 670 #define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 671 #define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L 672 //XPB_PIPE_STS 673 #define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 674 #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 675 #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 676 #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 677 #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 678 #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 679 #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 680 #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 681 #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 682 #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 683 #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 684 #define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 685 #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 686 #define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 687 #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL 688 #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L 689 #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 690 #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 691 #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 692 #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 693 #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 694 #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 695 #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 696 #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 697 #define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 698 #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L 699 //XPB_WCB_STS 700 #define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 701 #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 702 #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 703 #define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL 704 #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L 705 #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L 706 //XPB_MAP_INVERT_FLUSH_NUM_LSB 707 #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 708 #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL 709 //XPB_STICKY 710 #define XPB_STICKY__BITS__SHIFT 0x0 711 #define XPB_STICKY__BITS_MASK 0xFFFFFFFFL 712 //XPB_STICKY_W1C 713 #define XPB_STICKY_W1C__BITS__SHIFT 0x0 714 #define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL 715 //XPB_SUB_CTRL 716 #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 717 #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 718 #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 719 #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 720 #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 721 #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 722 #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 723 #define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 724 #define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 725 #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 726 #define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 727 #define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 728 #define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 729 #define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 730 #define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 731 #define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 732 #define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 733 #define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 734 #define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 735 #define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 736 #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 737 #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 738 #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 739 #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 740 #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 741 #define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 742 #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 743 #define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 744 #define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 745 #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 746 #define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 747 #define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 748 #define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 749 #define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 750 #define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 751 #define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 752 #define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 753 #define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 754 #define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 755 #define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 756 //XPB_PERF_KNOBS 757 #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 758 #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 759 #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 760 #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL 761 #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L 762 #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L 763 //XPB_MISC_CFG 764 #define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 765 #define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 766 #define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 767 #define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 768 #define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 769 #define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL 770 #define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L 771 #define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L 772 #define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L 773 #define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 774 //XPB_INTF_CFG2 775 #define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 776 #define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL 777 //XPB_CLG_EXTRA_RD 778 #define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 779 #define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 780 #define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb 781 #define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc 782 #define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf 783 #define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 784 #define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a 785 #define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b 786 #define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL 787 #define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L 788 #define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L 789 #define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L 790 #define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L 791 #define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L 792 #define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L 793 #define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L 794 //XPB_CLG_EXTRA_MSK_RD 795 #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 796 #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 797 #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb 798 #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 799 #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL 800 #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L 801 #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L 802 #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L 803 //XPB_CLG_GFX_MATCH 804 #define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 805 #define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x8 806 #define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0x10 807 #define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x18 808 #define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x000000FFL 809 #define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x0000FF00L 810 #define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x00FF0000L 811 #define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0xFF000000L 812 //XPB_CLG_GFX_MATCH_VLD 813 #define XPB_CLG_GFX_MATCH_VLD__FARBIRC0_VLD__SHIFT 0x0 814 #define XPB_CLG_GFX_MATCH_VLD__FARBIRC1_VLD__SHIFT 0x1 815 #define XPB_CLG_GFX_MATCH_VLD__FARBIRC2_VLD__SHIFT 0x2 816 #define XPB_CLG_GFX_MATCH_VLD__FARBIRC3_VLD__SHIFT 0x3 817 #define XPB_CLG_GFX_MATCH_VLD__FARBIRC0_VLD_MASK 0x00000001L 818 #define XPB_CLG_GFX_MATCH_VLD__FARBIRC1_VLD_MASK 0x00000002L 819 #define XPB_CLG_GFX_MATCH_VLD__FARBIRC2_VLD_MASK 0x00000004L 820 #define XPB_CLG_GFX_MATCH_VLD__FARBIRC3_VLD_MASK 0x00000008L 821 //XPB_CLG_GFX_MATCH_MSK 822 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 823 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x8 824 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0x10 825 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x18 826 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x000000FFL 827 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x0000FF00L 828 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x00FF0000L 829 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0xFF000000L 830 //XPB_CLG_MM_MATCH 831 #define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 832 #define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x8 833 #define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0x10 834 #define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x18 835 #define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x000000FFL 836 #define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x0000FF00L 837 #define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x00FF0000L 838 #define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0xFF000000L 839 //XPB_CLG_MM_MATCH_VLD 840 #define XPB_CLG_MM_MATCH_VLD__FARBIRC0_VLD__SHIFT 0x0 841 #define XPB_CLG_MM_MATCH_VLD__FARBIRC1_VLD__SHIFT 0x1 842 #define XPB_CLG_MM_MATCH_VLD__FARBIRC2_VLD__SHIFT 0x2 843 #define XPB_CLG_MM_MATCH_VLD__FARBIRC3_VLD__SHIFT 0x3 844 #define XPB_CLG_MM_MATCH_VLD__FARBIRC0_VLD_MASK 0x00000001L 845 #define XPB_CLG_MM_MATCH_VLD__FARBIRC1_VLD_MASK 0x00000002L 846 #define XPB_CLG_MM_MATCH_VLD__FARBIRC2_VLD_MASK 0x00000004L 847 #define XPB_CLG_MM_MATCH_VLD__FARBIRC3_VLD_MASK 0x00000008L 848 //XPB_CLG_MM_MATCH_MSK 849 #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 850 #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x8 851 #define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0x10 852 #define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x18 853 #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x000000FFL 854 #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x0000FF00L 855 #define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x00FF0000L 856 #define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0xFF000000L 857 //XPB_CLG_GFX_UNITID_MAPPING0 858 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 859 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 860 #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 861 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 862 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 863 #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 864 //XPB_CLG_GFX_UNITID_MAPPING1 865 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 866 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 867 #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 868 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 869 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 870 #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 871 //XPB_CLG_GFX_UNITID_MAPPING2 872 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 873 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 874 #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 875 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 876 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 877 #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 878 //XPB_CLG_GFX_UNITID_MAPPING3 879 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 880 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 881 #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 882 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 883 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 884 #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 885 //XPB_CLG_GFX_UNITID_MAPPING4 886 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 887 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 888 #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 889 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL 890 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L 891 #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L 892 //XPB_CLG_GFX_UNITID_MAPPING5 893 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 894 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 895 #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 896 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL 897 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L 898 #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L 899 //XPB_CLG_GFX_UNITID_MAPPING6 900 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 901 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 902 #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 903 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL 904 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L 905 #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L 906 //XPB_CLG_GFX_UNITID_MAPPING7 907 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 908 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 909 #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 910 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL 911 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L 912 #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L 913 //XPB_CLG_MM_UNITID_MAPPING0 914 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 915 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 916 #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 917 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 918 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 919 #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 920 //XPB_CLG_MM_UNITID_MAPPING1 921 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 922 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 923 #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 924 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 925 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 926 #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 927 //XPB_CLG_MM_UNITID_MAPPING2 928 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 929 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 930 #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 931 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 932 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 933 #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 934 //XPB_CLG_MM_UNITID_MAPPING3 935 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 936 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 937 #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 938 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 939 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 940 #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 941 942 943 // addressBlock: athub_rpbdec 944 //ATHUB_SHARED_VIRT_RESET_REQ 945 #define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 946 #define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 947 #define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL 948 #define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 949 //ATHUB_MEM_POWER_LS 950 #define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 951 #define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 952 #define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 953 #define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x0007FFC0L 954 //ATHUB_MISC_CNTL 955 #define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x0 956 #define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x6 957 #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x7 958 #define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x8 959 #define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x9 960 #define ATHUB_MISC_CNTL__ALWAYS_BUSY__SHIFT 0xf 961 #define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x10 962 #define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x11 963 #define ATHUB_MISC_CNTL__RPB_BUSY__SHIFT 0x12 964 #define ATHUB_MISC_CNTL__XPB_BUSY__SHIFT 0x13 965 #define ATHUB_MISC_CNTL__ATS_BUSY__SHIFT 0x14 966 #define ATHUB_MISC_CNTL__SDPNCS_BUSY__SHIFT 0x15 967 #define ATHUB_MISC_CNTL__DFPORT_BUSY__SHIFT 0x16 968 #define ATHUB_MISC_CNTL__SWITCH_CNTL__SHIFT 0x17 969 #define ATHUB_MISC_CNTL__LS_DELAY_ENABLE__SHIFT 0x18 970 #define ATHUB_MISC_CNTL__LS_DELAY_TIME__SHIFT 0x19 971 #define ATHUB_MISC_CNTL__RESETB_PG_CLK_GATING_ENABLE__SHIFT 0x1e 972 #define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x0000003FL 973 #define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00000040L 974 #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00000080L 975 #define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00000100L 976 #define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x00007E00L 977 #define ATHUB_MISC_CNTL__ALWAYS_BUSY_MASK 0x00008000L 978 #define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x00010000L 979 #define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x00020000L 980 #define ATHUB_MISC_CNTL__RPB_BUSY_MASK 0x00040000L 981 #define ATHUB_MISC_CNTL__XPB_BUSY_MASK 0x00080000L 982 #define ATHUB_MISC_CNTL__ATS_BUSY_MASK 0x00100000L 983 #define ATHUB_MISC_CNTL__SDPNCS_BUSY_MASK 0x00200000L 984 #define ATHUB_MISC_CNTL__DFPORT_BUSY_MASK 0x00400000L 985 #define ATHUB_MISC_CNTL__SWITCH_CNTL_MASK 0x00800000L 986 #define ATHUB_MISC_CNTL__LS_DELAY_ENABLE_MASK 0x01000000L 987 #define ATHUB_MISC_CNTL__LS_DELAY_TIME_MASK 0x3E000000L 988 #define ATHUB_MISC_CNTL__RESETB_PG_CLK_GATING_ENABLE_MASK 0x40000000L 989 //RPB_PASSPW_CONF 990 #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 991 #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 992 #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE__SHIFT 0x2 993 #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE_EN__SHIFT 0x3 994 #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE__SHIFT 0x4 995 #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE_EN__SHIFT 0x5 996 #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE__SHIFT 0x6 997 #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE_EN__SHIFT 0x7 998 #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE__SHIFT 0x8 999 #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE_EN__SHIFT 0x9 1000 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0xa 1001 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xb 1002 #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE__SHIFT 0xc 1003 #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd 1004 #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0xe 1005 #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0xf 1006 #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x10 1007 #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x11 1008 #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x12 1009 #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0x13 1010 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0x14 1011 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0x15 1012 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x16 1013 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x17 1014 #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L 1015 #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L 1016 #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE_MASK 0x00000004L 1017 #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE_EN_MASK 0x00000008L 1018 #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE_MASK 0x00000010L 1019 #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE_EN_MASK 0x00000020L 1020 #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE_MASK 0x00000040L 1021 #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE_EN_MASK 0x00000080L 1022 #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE_MASK 0x00000100L 1023 #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE_EN_MASK 0x00000200L 1024 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000400L 1025 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00000800L 1026 #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_MASK 0x00001000L 1027 #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L 1028 #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00004000L 1029 #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00008000L 1030 #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00010000L 1031 #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00020000L 1032 #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00040000L 1033 #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00080000L 1034 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00100000L 1035 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00200000L 1036 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00400000L 1037 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00800000L 1038 //RPB_BLOCKLEVEL_CONF 1039 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 1040 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x2 1041 #define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL__SHIFT 0x3 1042 #define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL__SHIFT 0x5 1043 #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x7 1044 #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x9 1045 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0xb 1046 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xd 1047 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xe 1048 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 1049 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0x11 1050 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x13 1051 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L 1052 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00000004L 1053 #define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL_MASK 0x00000018L 1054 #define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL_MASK 0x00000060L 1055 #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000180L 1056 #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x00000600L 1057 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00001800L 1058 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00002000L 1059 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x0000C000L 1060 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L 1061 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00060000L 1062 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00080000L 1063 //RPB_TAG_CONF 1064 #define RPB_TAG_CONF__RPB_IO_RD__SHIFT 0x0 1065 #define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0xa 1066 #define RPB_TAG_CONF__RPB_IO_MAX_LIMIT__SHIFT 0x14 1067 #define RPB_TAG_CONF__RPB_IO_RD_MASK 0x000003FFL 1068 #define RPB_TAG_CONF__RPB_IO_WR_MASK 0x000FFC00L 1069 #define RPB_TAG_CONF__RPB_IO_MAX_LIMIT_MASK 0x7FF00000L 1070 //RPB_ARB_CNTL 1071 #define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 1072 #define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 1073 #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 1074 #define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 1075 #define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 1076 #define RPB_ARB_CNTL__RPB_VC0_CRD__SHIFT 0x1a 1077 #define RPB_ARB_CNTL__DISABLE_FED__SHIFT 0x1f 1078 #define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL 1079 #define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L 1080 #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L 1081 #define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L 1082 #define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L 1083 #define RPB_ARB_CNTL__RPB_VC0_CRD_MASK 0x7C000000L 1084 #define RPB_ARB_CNTL__DISABLE_FED_MASK 0x80000000L 1085 //RPB_ARB_CNTL2 1086 #define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 1087 #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 1088 #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 1089 #define RPB_ARB_CNTL2__RPB_VC1_CRD__SHIFT 0x18 1090 #define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL 1091 #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L 1092 #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L 1093 #define RPB_ARB_CNTL2__RPB_VC1_CRD_MASK 0x1F000000L 1094 //RPB_BIF_CNTL 1095 #define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 1096 #define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 1097 #define RPB_BIF_CNTL__VC2_SWITCH_NUM__SHIFT 0x10 1098 #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN__SHIFT 0x18 1099 #define RPB_BIF_CNTL__TR_QOS_VC__SHIFT 0x19 1100 #define RPB_BIF_CNTL__RESERVE__SHIFT 0x1c 1101 #define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL 1102 #define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L 1103 #define RPB_BIF_CNTL__VC2_SWITCH_NUM_MASK 0x00FF0000L 1104 #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN_MASK 0x01000000L 1105 #define RPB_BIF_CNTL__TR_QOS_VC_MASK 0x0E000000L 1106 #define RPB_BIF_CNTL__RESERVE_MASK 0xF0000000L 1107 //RPB_BIF_CNTL2 1108 #define RPB_BIF_CNTL2__ARB_MODE__SHIFT 0x0 1109 #define RPB_BIF_CNTL2__DRAIN_VC_NUM__SHIFT 0x1 1110 #define RPB_BIF_CNTL2__SWITCH_ENABLE__SHIFT 0x3 1111 #define RPB_BIF_CNTL2__SWITCH_THRESHOLD__SHIFT 0x4 1112 #define RPB_BIF_CNTL2__PAGE_PRI_EN__SHIFT 0xc 1113 #define RPB_BIF_CNTL2__VC5_TR_PRI_EN__SHIFT 0xd 1114 #define RPB_BIF_CNTL2__VC0_TR_PRI_EN__SHIFT 0xe 1115 #define RPB_BIF_CNTL2__VC0_CHAINED_OVERRIDE__SHIFT 0xf 1116 #define RPB_BIF_CNTL2__VC1_CHAINED_OVERRIDE__SHIFT 0x10 1117 #define RPB_BIF_CNTL2__VC1_CHAINED_OVERRIDE_EN__SHIFT 0x11 1118 #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN__SHIFT 0x12 1119 #define RPB_BIF_CNTL2__ATHUB_NBIF_UNITID__SHIFT 0x13 1120 #define RPB_BIF_CNTL2__RESERVE__SHIFT 0x1e 1121 #define RPB_BIF_CNTL2__ARB_MODE_MASK 0x00000001L 1122 #define RPB_BIF_CNTL2__DRAIN_VC_NUM_MASK 0x00000006L 1123 #define RPB_BIF_CNTL2__SWITCH_ENABLE_MASK 0x00000008L 1124 #define RPB_BIF_CNTL2__SWITCH_THRESHOLD_MASK 0x00000FF0L 1125 #define RPB_BIF_CNTL2__PAGE_PRI_EN_MASK 0x00001000L 1126 #define RPB_BIF_CNTL2__VC5_TR_PRI_EN_MASK 0x00002000L 1127 #define RPB_BIF_CNTL2__VC0_TR_PRI_EN_MASK 0x00004000L 1128 #define RPB_BIF_CNTL2__VC0_CHAINED_OVERRIDE_MASK 0x00008000L 1129 #define RPB_BIF_CNTL2__VC1_CHAINED_OVERRIDE_MASK 0x00010000L 1130 #define RPB_BIF_CNTL2__VC1_CHAINED_OVERRIDE_EN_MASK 0x00020000L 1131 #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN_MASK 0x00040000L 1132 #define RPB_BIF_CNTL2__ATHUB_NBIF_UNITID_MASK 0x3FF80000L 1133 #define RPB_BIF_CNTL2__RESERVE_MASK 0xC0000000L 1134 //RPB_SDPPORT_CNTL 1135 #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 1136 #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 1137 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 1138 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 1139 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 1140 #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 1141 #define RPB_SDPPORT_CNTL__RESERVE1__SHIFT 0xa 1142 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 1143 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 1144 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 1145 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 1146 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 1147 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 1148 #define RPB_SDPPORT_CNTL__CG_BUSY_PORT__SHIFT 0x1c 1149 #define RPB_SDPPORT_CNTL__RESERVE__SHIFT 0x1d 1150 #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L 1151 #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L 1152 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L 1153 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L 1154 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L 1155 #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L 1156 #define RPB_SDPPORT_CNTL__RESERVE1_MASK 0x003FFC00L 1157 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 1158 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 1159 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 1160 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 1161 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 1162 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 1163 #define RPB_SDPPORT_CNTL__CG_BUSY_PORT_MASK 0x10000000L 1164 #define RPB_SDPPORT_CNTL__RESERVE_MASK 0xE0000000L 1165 //RPB_NBIF_SDPPORT_CNTL 1166 #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD__SHIFT 0x0 1167 #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD__SHIFT 0x8 1168 #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD__SHIFT 0x10 1169 #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD__SHIFT 0x18 1170 #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD_MASK 0x000000FFL 1171 #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD_MASK 0x0000FF00L 1172 #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD_MASK 0x00FF0000L 1173 #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD_MASK 0xFF000000L 1174 //RPB_DEINTRLV_COMBINE_CNTL 1175 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 1176 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 1177 #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 1178 #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD__SHIFT 0x6 1179 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN__SHIFT 0xe 1180 #define RPB_DEINTRLV_COMBINE_CNTL__RESERVE__SHIFT 0xf 1181 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL 1182 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L 1183 #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L 1184 #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD_MASK 0x00003FC0L 1185 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN_MASK 0x00004000L 1186 #define RPB_DEINTRLV_COMBINE_CNTL__RESERVE_MASK 0xFFFF8000L 1187 //RPB_VC_SWITCH_RDWR 1188 #define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 1189 #define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 1190 #define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa 1191 #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD__SHIFT 0x12 1192 #define RPB_VC_SWITCH_RDWR__CENTER_MARGIN__SHIFT 0x1a 1193 #define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L 1194 #define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL 1195 #define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L 1196 #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD_MASK 0x03FC0000L 1197 #define RPB_VC_SWITCH_RDWR__CENTER_MARGIN_MASK 0xFC000000L 1198 //RPB_ATS_CNTL3 1199 #define RPB_ATS_CNTL3__RPB_ATS_VC5_TR__SHIFT 0x0 1200 #define RPB_ATS_CNTL3__RPB_ATS_VC0_TR__SHIFT 0x9 1201 #define RPB_ATS_CNTL3__RPB_ATS_PR__SHIFT 0x12 1202 #define RPB_ATS_CNTL3__RPB_ATS_VC5_TR_MASK 0x000001FFL 1203 #define RPB_ATS_CNTL3__RPB_ATS_VC0_TR_MASK 0x0003FE00L 1204 #define RPB_ATS_CNTL3__RPB_ATS_PR_MASK 0x07FC0000L 1205 //RPB_DF_SDPPORT_CNTL 1206 #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD__SHIFT 0x0 1207 #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD__SHIFT 0x6 1208 #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD__SHIFT 0xe 1209 #define RPB_DF_SDPPORT_CNTL__DF_RELEASE_CREDIT_MODE__SHIFT 0x12 1210 #define RPB_DF_SDPPORT_CNTL__DF_ORIG_ACK_TIMER__SHIFT 0x13 1211 #define RPB_DF_SDPPORT_CNTL__DF_RAW_EA_CHECK_ENABLE__SHIFT 0x1b 1212 #define RPB_DF_SDPPORT_CNTL__DF_RAW_CHECK_ENABLE__SHIFT 0x1c 1213 #define RPB_DF_SDPPORT_CNTL__DF_RAAT_CHECK_ENABLE__SHIFT 0x1d 1214 #define RPB_DF_SDPPORT_CNTL__DF_ATAR_CHECK_ENABLE__SHIFT 0x1e 1215 #define RPB_DF_SDPPORT_CNTL__DF_VC3_READ_CHECK__SHIFT 0x1f 1216 #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD_MASK 0x0000003FL 1217 #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD_MASK 0x00003FC0L 1218 #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD_MASK 0x0003C000L 1219 #define RPB_DF_SDPPORT_CNTL__DF_RELEASE_CREDIT_MODE_MASK 0x00040000L 1220 #define RPB_DF_SDPPORT_CNTL__DF_ORIG_ACK_TIMER_MASK 0x07F80000L 1221 #define RPB_DF_SDPPORT_CNTL__DF_RAW_EA_CHECK_ENABLE_MASK 0x08000000L 1222 #define RPB_DF_SDPPORT_CNTL__DF_RAW_CHECK_ENABLE_MASK 0x10000000L 1223 #define RPB_DF_SDPPORT_CNTL__DF_RAAT_CHECK_ENABLE_MASK 0x20000000L 1224 #define RPB_DF_SDPPORT_CNTL__DF_ATAR_CHECK_ENABLE_MASK 0x40000000L 1225 #define RPB_DF_SDPPORT_CNTL__DF_VC3_READ_CHECK_MASK 0x80000000L 1226 //RPB_ATS_CNTL 1227 #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 1228 #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 1229 #define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 1230 #define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 1231 #define RPB_ATS_CNTL__ATCTR_VC0_SWITCH_NUM__SHIFT 0xf 1232 #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 1233 #define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 1234 #define RPB_ATS_CNTL__MM_TRANS_VC5_ENABLE__SHIFT 0x19 1235 #define RPB_ATS_CNTL__GC_TRANS_VC5_ENABLE__SHIFT 0x1a 1236 #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L 1237 #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L 1238 #define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL 1239 #define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L 1240 #define RPB_ATS_CNTL__ATCTR_VC0_SWITCH_NUM_MASK 0x00078000L 1241 #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L 1242 #define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L 1243 #define RPB_ATS_CNTL__MM_TRANS_VC5_ENABLE_MASK 0x02000000L 1244 #define RPB_ATS_CNTL__GC_TRANS_VC5_ENABLE_MASK 0x04000000L 1245 //RPB_ATS_CNTL2 1246 #define RPB_ATS_CNTL2__INVAL_COM_CMD__SHIFT 0x0 1247 #define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x6 1248 #define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0xc 1249 #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0x12 1250 #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0x15 1251 #define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x18 1252 #define RPB_ATS_CNTL2__RPB_VC5_CRD__SHIFT 0x1a 1253 #define RPB_ATS_CNTL2__INVAL_COM_CMD_MASK 0x0000003FL 1254 #define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x00000FC0L 1255 #define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x0003F000L 1256 #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x001C0000L 1257 #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00E00000L 1258 #define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x03000000L 1259 #define RPB_ATS_CNTL2__RPB_VC5_CRD_MASK 0x7C000000L 1260 //RPB_PERFCOUNTER0_CFG 1261 #define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1262 #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1263 #define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1264 #define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1265 #define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1266 #define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1267 #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1268 #define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1269 #define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1270 #define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1271 //RPB_PERFCOUNTER1_CFG 1272 #define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1273 #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1274 #define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1275 #define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1276 #define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1277 #define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1278 #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1279 #define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1280 #define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1281 #define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1282 //RPB_PERFCOUNTER2_CFG 1283 #define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1284 #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1285 #define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1286 #define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1287 #define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1288 #define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1289 #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1290 #define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1291 #define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1292 #define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1293 //RPB_PERFCOUNTER3_CFG 1294 #define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 1295 #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 1296 #define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 1297 #define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 1298 #define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 1299 #define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 1300 #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 1301 #define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 1302 #define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 1303 #define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 1304 //RPB_PERFCOUNTER_RSLT_CNTL 1305 #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1306 #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1307 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1308 #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1309 #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1310 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1311 #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1312 #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1313 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1314 #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1315 #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1316 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1317 //RPB_PERF_COUNTER_CNTL 1318 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1319 #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 1320 #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 1321 #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 1322 #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 1323 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 1324 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe 1325 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 1326 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 1327 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 1328 #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L 1329 #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L 1330 #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L 1331 #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001E0L 1332 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003E00L 1333 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007C000L 1334 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00F80000L 1335 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1F000000L 1336 //RPB_PERFCOUNTER_HI 1337 #define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1338 #define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1339 #define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1340 #define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1341 //RPB_PERFCOUNTER_LO 1342 #define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1343 #define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1344 //RPB_PERF_COUNTER_STATUS 1345 #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 1346 #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xFFFFFFFFL 1347 1348 #endif 1349