1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HyperV Detection code. 4 * 5 * Copyright (C) 2010, Novell, Inc. 6 * Author : K. Y. Srinivasan <ksrinivasan@novell.com> 7 */ 8 9 #include <linux/types.h> 10 #include <linux/time.h> 11 #include <linux/clocksource.h> 12 #include <linux/init.h> 13 #include <linux/export.h> 14 #include <linux/hardirq.h> 15 #include <linux/efi.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/kexec.h> 19 #include <linux/random.h> 20 #include <asm/processor.h> 21 #include <asm/hypervisor.h> 22 #include <asm/hyperv-tlfs.h> 23 #include <asm/mshyperv.h> 24 #include <asm/desc.h> 25 #include <asm/idtentry.h> 26 #include <asm/irq_regs.h> 27 #include <asm/i8259.h> 28 #include <asm/apic.h> 29 #include <asm/timer.h> 30 #include <asm/reboot.h> 31 #include <asm/nmi.h> 32 #include <clocksource/hyperv_timer.h> 33 #include <asm/numa.h> 34 #include <asm/svm.h> 35 36 /* Is Linux running as the root partition? */ 37 bool hv_root_partition; 38 /* Is Linux running on nested Microsoft Hypervisor */ 39 bool hv_nested; 40 struct ms_hyperv_info ms_hyperv; 41 42 /* Used in modules via hv_do_hypercall(): see arch/x86/include/asm/mshyperv.h */ 43 bool hyperv_paravisor_present __ro_after_init; 44 EXPORT_SYMBOL_GPL(hyperv_paravisor_present); 45 46 #if IS_ENABLED(CONFIG_HYPERV) hv_get_nested_msr(unsigned int reg)47 static inline unsigned int hv_get_nested_msr(unsigned int reg) 48 { 49 if (hv_is_sint_msr(reg)) 50 return reg - HV_X64_MSR_SINT0 + HV_X64_MSR_NESTED_SINT0; 51 52 switch (reg) { 53 case HV_X64_MSR_SIMP: 54 return HV_X64_MSR_NESTED_SIMP; 55 case HV_X64_MSR_SIEFP: 56 return HV_X64_MSR_NESTED_SIEFP; 57 case HV_X64_MSR_SVERSION: 58 return HV_X64_MSR_NESTED_SVERSION; 59 case HV_X64_MSR_SCONTROL: 60 return HV_X64_MSR_NESTED_SCONTROL; 61 case HV_X64_MSR_EOM: 62 return HV_X64_MSR_NESTED_EOM; 63 default: 64 return reg; 65 } 66 } 67 hv_get_non_nested_msr(unsigned int reg)68 u64 hv_get_non_nested_msr(unsigned int reg) 69 { 70 u64 value; 71 72 if (hv_is_synic_msr(reg) && ms_hyperv.paravisor_present) 73 hv_ivm_msr_read(reg, &value); 74 else 75 rdmsrl(reg, value); 76 return value; 77 } 78 EXPORT_SYMBOL_GPL(hv_get_non_nested_msr); 79 hv_set_non_nested_msr(unsigned int reg,u64 value)80 void hv_set_non_nested_msr(unsigned int reg, u64 value) 81 { 82 if (hv_is_synic_msr(reg) && ms_hyperv.paravisor_present) { 83 hv_ivm_msr_write(reg, value); 84 85 /* Write proxy bit via wrmsl instruction */ 86 if (hv_is_sint_msr(reg)) 87 wrmsrl(reg, value | 1 << 20); 88 } else { 89 wrmsrl(reg, value); 90 } 91 } 92 EXPORT_SYMBOL_GPL(hv_set_non_nested_msr); 93 hv_get_msr(unsigned int reg)94 u64 hv_get_msr(unsigned int reg) 95 { 96 if (hv_nested) 97 reg = hv_get_nested_msr(reg); 98 99 return hv_get_non_nested_msr(reg); 100 } 101 EXPORT_SYMBOL_GPL(hv_get_msr); 102 hv_set_msr(unsigned int reg,u64 value)103 void hv_set_msr(unsigned int reg, u64 value) 104 { 105 if (hv_nested) 106 reg = hv_get_nested_msr(reg); 107 108 hv_set_non_nested_msr(reg, value); 109 } 110 EXPORT_SYMBOL_GPL(hv_set_msr); 111 112 static void (*vmbus_handler)(void); 113 static void (*hv_stimer0_handler)(void); 114 static void (*hv_kexec_handler)(void); 115 static void (*hv_crash_handler)(struct pt_regs *regs); 116 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback)117 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_callback) 118 { 119 struct pt_regs *old_regs = set_irq_regs(regs); 120 121 inc_irq_stat(irq_hv_callback_count); 122 if (vmbus_handler) 123 vmbus_handler(); 124 125 if (ms_hyperv.hints & HV_DEPRECATING_AEOI_RECOMMENDED) 126 apic_eoi(); 127 128 set_irq_regs(old_regs); 129 } 130 hv_setup_vmbus_handler(void (* handler)(void))131 void hv_setup_vmbus_handler(void (*handler)(void)) 132 { 133 vmbus_handler = handler; 134 } 135 hv_remove_vmbus_handler(void)136 void hv_remove_vmbus_handler(void) 137 { 138 /* We have no way to deallocate the interrupt gate */ 139 vmbus_handler = NULL; 140 } 141 142 /* 143 * Routines to do per-architecture handling of stimer0 144 * interrupts when in Direct Mode 145 */ DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0)146 DEFINE_IDTENTRY_SYSVEC(sysvec_hyperv_stimer0) 147 { 148 struct pt_regs *old_regs = set_irq_regs(regs); 149 150 inc_irq_stat(hyperv_stimer0_count); 151 if (hv_stimer0_handler) 152 hv_stimer0_handler(); 153 add_interrupt_randomness(HYPERV_STIMER0_VECTOR); 154 apic_eoi(); 155 156 set_irq_regs(old_regs); 157 } 158 159 /* For x86/x64, override weak placeholders in hyperv_timer.c */ hv_setup_stimer0_handler(void (* handler)(void))160 void hv_setup_stimer0_handler(void (*handler)(void)) 161 { 162 hv_stimer0_handler = handler; 163 } 164 hv_remove_stimer0_handler(void)165 void hv_remove_stimer0_handler(void) 166 { 167 /* We have no way to deallocate the interrupt gate */ 168 hv_stimer0_handler = NULL; 169 } 170 hv_setup_kexec_handler(void (* handler)(void))171 void hv_setup_kexec_handler(void (*handler)(void)) 172 { 173 hv_kexec_handler = handler; 174 } 175 hv_remove_kexec_handler(void)176 void hv_remove_kexec_handler(void) 177 { 178 hv_kexec_handler = NULL; 179 } 180 hv_setup_crash_handler(void (* handler)(struct pt_regs * regs))181 void hv_setup_crash_handler(void (*handler)(struct pt_regs *regs)) 182 { 183 hv_crash_handler = handler; 184 } 185 hv_remove_crash_handler(void)186 void hv_remove_crash_handler(void) 187 { 188 hv_crash_handler = NULL; 189 } 190 191 #ifdef CONFIG_KEXEC_CORE hv_machine_shutdown(void)192 static void hv_machine_shutdown(void) 193 { 194 if (kexec_in_progress && hv_kexec_handler) 195 hv_kexec_handler(); 196 197 /* 198 * Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor 199 * corrupts the old VP Assist Pages and can crash the kexec kernel. 200 */ 201 if (kexec_in_progress) 202 cpuhp_remove_state(CPUHP_AP_HYPERV_ONLINE); 203 204 /* The function calls stop_other_cpus(). */ 205 native_machine_shutdown(); 206 207 /* Disable the hypercall page when there is only 1 active CPU. */ 208 if (kexec_in_progress) 209 hyperv_cleanup(); 210 } 211 #endif /* CONFIG_KEXEC_CORE */ 212 213 #ifdef CONFIG_CRASH_DUMP hv_machine_crash_shutdown(struct pt_regs * regs)214 static void hv_machine_crash_shutdown(struct pt_regs *regs) 215 { 216 if (hv_crash_handler) 217 hv_crash_handler(regs); 218 219 /* The function calls crash_smp_send_stop(). */ 220 native_machine_crash_shutdown(regs); 221 222 /* Disable the hypercall page when there is only 1 active CPU. */ 223 hyperv_cleanup(); 224 } 225 #endif /* CONFIG_CRASH_DUMP */ 226 #endif /* CONFIG_HYPERV */ 227 ms_hyperv_platform(void)228 static uint32_t __init ms_hyperv_platform(void) 229 { 230 u32 eax; 231 u32 hyp_signature[3]; 232 233 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) 234 return 0; 235 236 cpuid(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS, 237 &eax, &hyp_signature[0], &hyp_signature[1], &hyp_signature[2]); 238 239 if (eax < HYPERV_CPUID_MIN || eax > HYPERV_CPUID_MAX || 240 memcmp("Microsoft Hv", hyp_signature, 12)) 241 return 0; 242 243 /* HYPERCALL and VP_INDEX MSRs are mandatory for all features. */ 244 eax = cpuid_eax(HYPERV_CPUID_FEATURES); 245 if (!(eax & HV_MSR_HYPERCALL_AVAILABLE)) { 246 pr_warn("x86/hyperv: HYPERCALL MSR not available.\n"); 247 return 0; 248 } 249 if (!(eax & HV_MSR_VP_INDEX_AVAILABLE)) { 250 pr_warn("x86/hyperv: VP_INDEX MSR not available.\n"); 251 return 0; 252 } 253 254 return HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS; 255 } 256 257 #ifdef CONFIG_X86_LOCAL_APIC 258 /* 259 * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes 260 * it difficult to process CHANNELMSG_UNLOAD in case of crash. Handle 261 * unknown NMI on the first CPU which gets it. 262 */ hv_nmi_unknown(unsigned int val,struct pt_regs * regs)263 static int hv_nmi_unknown(unsigned int val, struct pt_regs *regs) 264 { 265 static atomic_t nmi_cpu = ATOMIC_INIT(-1); 266 unsigned int old_cpu, this_cpu; 267 268 if (!unknown_nmi_panic) 269 return NMI_DONE; 270 271 old_cpu = -1; 272 this_cpu = raw_smp_processor_id(); 273 if (!atomic_try_cmpxchg(&nmi_cpu, &old_cpu, this_cpu)) 274 return NMI_HANDLED; 275 276 return NMI_DONE; 277 } 278 #endif 279 hv_get_tsc_khz(void)280 static unsigned long hv_get_tsc_khz(void) 281 { 282 unsigned long freq; 283 284 rdmsrl(HV_X64_MSR_TSC_FREQUENCY, freq); 285 286 return freq / 1000; 287 } 288 289 #if defined(CONFIG_SMP) && IS_ENABLED(CONFIG_HYPERV) hv_smp_prepare_boot_cpu(void)290 static void __init hv_smp_prepare_boot_cpu(void) 291 { 292 native_smp_prepare_boot_cpu(); 293 #if defined(CONFIG_X86_64) && defined(CONFIG_PARAVIRT_SPINLOCKS) 294 hv_init_spinlocks(); 295 #endif 296 } 297 hv_smp_prepare_cpus(unsigned int max_cpus)298 static void __init hv_smp_prepare_cpus(unsigned int max_cpus) 299 { 300 #ifdef CONFIG_X86_64 301 int i; 302 int ret; 303 #endif 304 305 native_smp_prepare_cpus(max_cpus); 306 307 /* 308 * Override wakeup_secondary_cpu_64 callback for SEV-SNP 309 * enlightened guest. 310 */ 311 if (!ms_hyperv.paravisor_present && hv_isolation_type_snp()) { 312 apic->wakeup_secondary_cpu_64 = hv_snp_boot_ap; 313 return; 314 } 315 316 #ifdef CONFIG_X86_64 317 for_each_present_cpu(i) { 318 if (i == 0) 319 continue; 320 ret = hv_call_add_logical_proc(numa_cpu_node(i), i, cpu_physical_id(i)); 321 BUG_ON(ret); 322 } 323 324 for_each_present_cpu(i) { 325 if (i == 0) 326 continue; 327 ret = hv_call_create_vp(numa_cpu_node(i), hv_current_partition_id, i, i); 328 BUG_ON(ret); 329 } 330 #endif 331 } 332 #endif 333 334 /* 335 * When a fully enlightened TDX VM runs on Hyper-V, the firmware sets the 336 * HW_REDUCED flag: refer to acpi_tb_create_local_fadt(). Consequently ttyS0 337 * interrupts can't work because request_irq() -> ... -> irq_to_desc() returns 338 * NULL for ttyS0. This happens because mp_config_acpi_legacy_irqs() sees a 339 * nr_legacy_irqs() of 0, so it doesn't initialize the array 'mp_irqs[]', and 340 * later setup_IO_APIC_irqs() -> find_irq_entry() fails to find the legacy irqs 341 * from the array and hence doesn't create the necessary irq description info. 342 * 343 * Clone arch/x86/kernel/acpi/boot.c: acpi_generic_reduced_hw_init() here, 344 * except don't change 'legacy_pic', which keeps its default value 345 * 'default_legacy_pic'. This way, mp_config_acpi_legacy_irqs() sees a non-zero 346 * nr_legacy_irqs() and eventually serial console interrupts works properly. 347 */ reduced_hw_init(void)348 static void __init reduced_hw_init(void) 349 { 350 x86_init.timers.timer_init = x86_init_noop; 351 x86_init.irqs.pre_vector_init = x86_init_noop; 352 } 353 hv_get_hypervisor_version(union hv_hypervisor_version_info * info)354 int hv_get_hypervisor_version(union hv_hypervisor_version_info *info) 355 { 356 unsigned int hv_max_functions; 357 358 hv_max_functions = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 359 if (hv_max_functions < HYPERV_CPUID_VERSION) { 360 pr_err("%s: Could not detect Hyper-V version\n", __func__); 361 return -ENODEV; 362 } 363 364 cpuid(HYPERV_CPUID_VERSION, &info->eax, &info->ebx, &info->ecx, &info->edx); 365 366 return 0; 367 } 368 ms_hyperv_init_platform(void)369 static void __init ms_hyperv_init_platform(void) 370 { 371 int hv_max_functions_eax; 372 373 #ifdef CONFIG_PARAVIRT 374 pv_info.name = "Hyper-V"; 375 #endif 376 377 /* 378 * Extract the features and hints 379 */ 380 ms_hyperv.features = cpuid_eax(HYPERV_CPUID_FEATURES); 381 ms_hyperv.priv_high = cpuid_ebx(HYPERV_CPUID_FEATURES); 382 ms_hyperv.misc_features = cpuid_edx(HYPERV_CPUID_FEATURES); 383 ms_hyperv.hints = cpuid_eax(HYPERV_CPUID_ENLIGHTMENT_INFO); 384 385 hv_max_functions_eax = cpuid_eax(HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS); 386 387 pr_info("Hyper-V: privilege flags low 0x%x, high 0x%x, hints 0x%x, misc 0x%x\n", 388 ms_hyperv.features, ms_hyperv.priv_high, ms_hyperv.hints, 389 ms_hyperv.misc_features); 390 391 ms_hyperv.max_vp_index = cpuid_eax(HYPERV_CPUID_IMPLEMENT_LIMITS); 392 ms_hyperv.max_lp_index = cpuid_ebx(HYPERV_CPUID_IMPLEMENT_LIMITS); 393 394 pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n", 395 ms_hyperv.max_vp_index, ms_hyperv.max_lp_index); 396 397 /* 398 * Check CPU management privilege. 399 * 400 * To mirror what Windows does we should extract CPU management 401 * features and use the ReservedIdentityBit to detect if Linux is the 402 * root partition. But that requires negotiating CPU management 403 * interface (a process to be finalized). For now, use the privilege 404 * flag as the indicator for running as root. 405 * 406 * Hyper-V should never specify running as root and as a Confidential 407 * VM. But to protect against a compromised/malicious Hyper-V trying 408 * to exploit root behavior to expose Confidential VM memory, ignore 409 * the root partition setting if also a Confidential VM. 410 */ 411 if ((ms_hyperv.priv_high & HV_CPU_MANAGEMENT) && 412 !(ms_hyperv.priv_high & HV_ISOLATION)) { 413 hv_root_partition = true; 414 pr_info("Hyper-V: running as root partition\n"); 415 } 416 417 if (ms_hyperv.hints & HV_X64_HYPERV_NESTED) { 418 hv_nested = true; 419 pr_info("Hyper-V: running on a nested hypervisor\n"); 420 } 421 422 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 423 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 424 x86_platform.calibrate_tsc = hv_get_tsc_khz; 425 x86_platform.calibrate_cpu = hv_get_tsc_khz; 426 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); 427 } 428 429 if (ms_hyperv.priv_high & HV_ISOLATION) { 430 ms_hyperv.isolation_config_a = cpuid_eax(HYPERV_CPUID_ISOLATION_CONFIG); 431 ms_hyperv.isolation_config_b = cpuid_ebx(HYPERV_CPUID_ISOLATION_CONFIG); 432 433 if (ms_hyperv.shared_gpa_boundary_active) 434 ms_hyperv.shared_gpa_boundary = 435 BIT_ULL(ms_hyperv.shared_gpa_boundary_bits); 436 437 hyperv_paravisor_present = !!ms_hyperv.paravisor_present; 438 439 pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n", 440 ms_hyperv.isolation_config_a, ms_hyperv.isolation_config_b); 441 442 443 if (hv_get_isolation_type() == HV_ISOLATION_TYPE_SNP) { 444 static_branch_enable(&isolation_type_snp); 445 } else if (hv_get_isolation_type() == HV_ISOLATION_TYPE_TDX) { 446 static_branch_enable(&isolation_type_tdx); 447 448 /* A TDX VM must use x2APIC and doesn't use lazy EOI. */ 449 ms_hyperv.hints &= ~HV_X64_APIC_ACCESS_RECOMMENDED; 450 451 if (!ms_hyperv.paravisor_present) { 452 /* 453 * Mark the Hyper-V TSC page feature as disabled 454 * in a TDX VM without paravisor so that the 455 * Invariant TSC, which is a better clocksource 456 * anyway, is used instead. 457 */ 458 ms_hyperv.features &= ~HV_MSR_REFERENCE_TSC_AVAILABLE; 459 460 /* 461 * The Invariant TSC is expected to be available 462 * in a TDX VM without paravisor, but if not, 463 * print a warning message. The slower Hyper-V MSR-based 464 * Ref Counter should end up being the clocksource. 465 */ 466 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 467 pr_warn("Hyper-V: Invariant TSC is unavailable\n"); 468 469 /* HV_MSR_CRASH_CTL is unsupported. */ 470 ms_hyperv.misc_features &= ~HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE; 471 472 /* Don't trust Hyper-V's TLB-flushing hypercalls. */ 473 ms_hyperv.hints &= ~HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED; 474 475 x86_init.acpi.reduced_hw_early_init = reduced_hw_init; 476 } 477 } 478 } 479 480 if (hv_max_functions_eax >= HYPERV_CPUID_NESTED_FEATURES) { 481 ms_hyperv.nested_features = 482 cpuid_eax(HYPERV_CPUID_NESTED_FEATURES); 483 pr_info("Hyper-V: Nested features: 0x%x\n", 484 ms_hyperv.nested_features); 485 } 486 487 #ifdef CONFIG_X86_LOCAL_APIC 488 if (ms_hyperv.features & HV_ACCESS_FREQUENCY_MSRS && 489 ms_hyperv.misc_features & HV_FEATURE_FREQUENCY_MSRS_AVAILABLE) { 490 /* 491 * Get the APIC frequency. 492 */ 493 u64 hv_lapic_frequency; 494 495 rdmsrl(HV_X64_MSR_APIC_FREQUENCY, hv_lapic_frequency); 496 hv_lapic_frequency = div_u64(hv_lapic_frequency, HZ); 497 lapic_timer_period = hv_lapic_frequency; 498 pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n", 499 lapic_timer_period); 500 } 501 502 register_nmi_handler(NMI_UNKNOWN, hv_nmi_unknown, NMI_FLAG_FIRST, 503 "hv_nmi_unknown"); 504 #endif 505 506 #ifdef CONFIG_X86_IO_APIC 507 no_timer_check = 1; 508 #endif 509 510 #if IS_ENABLED(CONFIG_HYPERV) 511 #if defined(CONFIG_KEXEC_CORE) 512 machine_ops.shutdown = hv_machine_shutdown; 513 #endif 514 #if defined(CONFIG_CRASH_DUMP) 515 machine_ops.crash_shutdown = hv_machine_crash_shutdown; 516 #endif 517 #endif 518 if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) { 519 /* 520 * Writing to synthetic MSR 0x40000118 updates/changes the 521 * guest visible CPUIDs. Setting bit 0 of this MSR enables 522 * guests to report invariant TSC feature through CPUID 523 * instruction, CPUID 0x800000007/EDX, bit 8. See code in 524 * early_init_intel() where this bit is examined. The 525 * setting of this MSR bit should happen before init_intel() 526 * is called. 527 */ 528 wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, HV_EXPOSE_INVARIANT_TSC); 529 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 530 } 531 532 /* 533 * Generation 2 instances don't support reading the NMI status from 534 * 0x61 port. 535 */ 536 if (efi_enabled(EFI_BOOT)) 537 x86_platform.get_nmi_reason = hv_get_nmi_reason; 538 539 #if IS_ENABLED(CONFIG_HYPERV) 540 if ((hv_get_isolation_type() == HV_ISOLATION_TYPE_VBS) || 541 ms_hyperv.paravisor_present) 542 hv_vtom_init(); 543 /* 544 * Setup the hook to get control post apic initialization. 545 */ 546 x86_platform.apic_post_init = hyperv_init; 547 hyperv_setup_mmu_ops(); 548 549 /* Install system interrupt handler for hypervisor callback */ 550 sysvec_install(HYPERVISOR_CALLBACK_VECTOR, sysvec_hyperv_callback); 551 552 /* Install system interrupt handler for reenlightenment notifications */ 553 if (ms_hyperv.features & HV_ACCESS_REENLIGHTENMENT) { 554 sysvec_install(HYPERV_REENLIGHTENMENT_VECTOR, sysvec_hyperv_reenlightenment); 555 } 556 557 /* Install system interrupt handler for stimer0 */ 558 if (ms_hyperv.misc_features & HV_STIMER_DIRECT_MODE_AVAILABLE) { 559 sysvec_install(HYPERV_STIMER0_VECTOR, sysvec_hyperv_stimer0); 560 } 561 562 # ifdef CONFIG_SMP 563 smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu; 564 if (hv_root_partition || 565 (!ms_hyperv.paravisor_present && hv_isolation_type_snp())) 566 smp_ops.smp_prepare_cpus = hv_smp_prepare_cpus; 567 # endif 568 569 /* 570 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic, 571 * set x2apic destination mode to physical mode when x2apic is available 572 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs 573 * have 8-bit APIC id. 574 */ 575 # ifdef CONFIG_X86_X2APIC 576 if (x2apic_supported()) 577 x2apic_phys = 1; 578 # endif 579 580 /* Register Hyper-V specific clocksource */ 581 hv_init_clocksource(); 582 hv_vtl_init_platform(); 583 #endif 584 /* 585 * TSC should be marked as unstable only after Hyper-V 586 * clocksource has been initialized. This ensures that the 587 * stability of the sched_clock is not altered. 588 */ 589 if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT)) 590 mark_tsc_unstable("running on Hyper-V"); 591 592 hardlockup_detector_disable(); 593 } 594 ms_hyperv_x2apic_available(void)595 static bool __init ms_hyperv_x2apic_available(void) 596 { 597 return x2apic_supported(); 598 } 599 600 /* 601 * If ms_hyperv_msi_ext_dest_id() returns true, hyperv_prepare_irq_remapping() 602 * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the 603 * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg(). 604 * 605 * Note: for a VM on Hyper-V, the I/O-APIC is the only device which 606 * (logically) generates MSIs directly to the system APIC irq domain. 607 * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the 608 * pci-hyperv host bridge. 609 * 610 * Note: for a Hyper-V root partition, this will always return false. 611 * The hypervisor doesn't expose these HYPERV_CPUID_VIRT_STACK_* cpuids by 612 * default, they are implemented as intercepts by the Windows Hyper-V stack. 613 * Even a nested root partition (L2 root) will not get them because the 614 * nested (L1) hypervisor filters them out. 615 */ ms_hyperv_msi_ext_dest_id(void)616 static bool __init ms_hyperv_msi_ext_dest_id(void) 617 { 618 u32 eax; 619 620 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_INTERFACE); 621 if (eax != HYPERV_VS_INTERFACE_EAX_SIGNATURE) 622 return false; 623 624 eax = cpuid_eax(HYPERV_CPUID_VIRT_STACK_PROPERTIES); 625 return eax & HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE; 626 } 627 628 #ifdef CONFIG_AMD_MEM_ENCRYPT hv_sev_es_hcall_prepare(struct ghcb * ghcb,struct pt_regs * regs)629 static void hv_sev_es_hcall_prepare(struct ghcb *ghcb, struct pt_regs *regs) 630 { 631 /* RAX and CPL are already in the GHCB */ 632 ghcb_set_rcx(ghcb, regs->cx); 633 ghcb_set_rdx(ghcb, regs->dx); 634 ghcb_set_r8(ghcb, regs->r8); 635 } 636 hv_sev_es_hcall_finish(struct ghcb * ghcb,struct pt_regs * regs)637 static bool hv_sev_es_hcall_finish(struct ghcb *ghcb, struct pt_regs *regs) 638 { 639 /* No checking of the return state needed */ 640 return true; 641 } 642 #endif 643 644 const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = { 645 .name = "Microsoft Hyper-V", 646 .detect = ms_hyperv_platform, 647 .type = X86_HYPER_MS_HYPERV, 648 .init.x2apic_available = ms_hyperv_x2apic_available, 649 .init.msi_ext_dest_id = ms_hyperv_msi_ext_dest_id, 650 .init.init_platform = ms_hyperv_init_platform, 651 .init.guest_late_init = ms_hyperv_late_init, 652 #ifdef CONFIG_AMD_MEM_ENCRYPT 653 .runtime.sev_es_hcall_prepare = hv_sev_es_hcall_prepare, 654 .runtime.sev_es_hcall_finish = hv_sev_es_hcall_finish, 655 #endif 656 }; 657