1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/asm/pgtable-2level.h 4 * 5 * Copyright (C) 1995-2002 Russell King 6 */ 7 #ifndef _ASM_PGTABLE_2LEVEL_H 8 #define _ASM_PGTABLE_2LEVEL_H 9 10 #define __PAGETABLE_PMD_FOLDED 1 11 12 /* 13 * Hardware-wise, we have a two level page table structure, where the first 14 * level has 4096 entries, and the second level has 256 entries. Each entry 15 * is one 32-bit word. Most of the bits in the second level entry are used 16 * by hardware, and there aren't any "accessed" and "dirty" bits. 17 * 18 * Linux on the other hand has a three level page table structure, which can 19 * be wrapped to fit a two level page table structure easily - using the PGD 20 * and PTE only. However, Linux also expects one "PTE" table per page, and 21 * at least a "dirty" bit. 22 * 23 * Therefore, we tweak the implementation slightly - we tell Linux that we 24 * have 2048 entries in the first level, each of which is 8 bytes (iow, two 25 * hardware pointers to the second level.) The second level contains two 26 * hardware PTE tables arranged contiguously, preceded by Linux versions 27 * which contain the state information Linux needs. We, therefore, end up 28 * with 512 entries in the "PTE" level. 29 * 30 * This leads to the page tables having the following layout: 31 * 32 * pgd pte 33 * | | 34 * +--------+ 35 * | | +------------+ +0 36 * +- - - - + | Linux pt 0 | 37 * | | +------------+ +1024 38 * +--------+ +0 | Linux pt 1 | 39 * | |-----> +------------+ +2048 40 * +- - - - + +4 | h/w pt 0 | 41 * | |-----> +------------+ +3072 42 * +--------+ +8 | h/w pt 1 | 43 * | | +------------+ +4096 44 * 45 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and 46 * PTE_xxx for definitions of bits appearing in the "h/w pt". 47 * 48 * PMD_xxx definitions refer to bits in the first level page table. 49 * 50 * The "dirty" bit is emulated by only granting hardware write permission 51 * iff the page is marked "writable" and "dirty" in the Linux PTE. This 52 * means that a write to a clean page will cause a permission fault, and 53 * the Linux MM layer will mark the page dirty via handle_pte_fault(). 54 * For the hardware to notice the permission change, the TLB entry must 55 * be flushed, and ptep_set_access_flags() does that for us. 56 * 57 * The "accessed" or "young" bit is emulated by a similar method; we only 58 * allow accesses to the page if the "young" bit is set. Accesses to the 59 * page will cause a fault, and handle_pte_fault() will set the young bit 60 * for us as long as the page is marked present in the corresponding Linux 61 * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is 62 * up to date. 63 * 64 * However, when the "young" bit is cleared, we deny access to the page 65 * by clearing the hardware PTE. Currently Linux does not flush the TLB 66 * for us in this case, which means the TLB will retain the transation 67 * until either the TLB entry is evicted under pressure, or a context 68 * switch which changes the user space mapping occurs. 69 */ 70 #define PTRS_PER_PTE 512 71 #define PTRS_PER_PMD 1 72 #define PTRS_PER_PGD 2048 73 74 #define PTE_HWTABLE_PTRS (PTRS_PER_PTE) 75 #define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) 76 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) 77 78 #define MAX_POSSIBLE_PHYSMEM_BITS 32 79 80 /* 81 * PMD_SHIFT determines the size of the area a second-level page table can map 82 * PGDIR_SHIFT determines what a third-level page table entry can map 83 */ 84 #define PMD_SHIFT 21 85 #define PGDIR_SHIFT 21 86 87 #define PMD_SIZE (1UL << PMD_SHIFT) 88 #define PMD_MASK (~(PMD_SIZE-1)) 89 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 90 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 91 92 /* 93 * section address mask and size definitions. 94 */ 95 #define SECTION_SHIFT 20 96 #define SECTION_SIZE (1UL << SECTION_SHIFT) 97 #define SECTION_MASK (~(SECTION_SIZE-1)) 98 99 /* 100 * ARMv6 supersection address mask and size definitions. 101 */ 102 #define SUPERSECTION_SHIFT 24 103 #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) 104 #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) 105 106 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 107 108 /* 109 * "Linux" PTE definitions. 110 * 111 * We keep two sets of PTEs - the hardware and the linux version. 112 * This allows greater flexibility in the way we map the Linux bits 113 * onto the hardware tables, and allows us to have YOUNG and DIRTY 114 * bits. 115 * 116 * The PTE table pointer refers to the hardware entries; the "Linux" 117 * entries are stored 1024 bytes below. 118 */ 119 #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ 120 #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) 121 #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) 122 #define L_PTE_DIRTY (_AT(pteval_t, 1) << 6) 123 #define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) 124 #define L_PTE_USER (_AT(pteval_t, 1) << 8) 125 #define L_PTE_XN (_AT(pteval_t, 1) << 9) 126 #define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */ 127 #define L_PTE_NONE (_AT(pteval_t, 1) << 11) 128 129 /* We borrow bit 7 to store the exclusive marker in swap PTEs. */ 130 #define L_PTE_SWP_EXCLUSIVE L_PTE_RDONLY 131 132 /* 133 * These are the memory types, defined to be compatible with 134 * pre-ARMv6 CPUs cacheable and bufferable bits: n/a,n/a,C,B 135 * ARMv6+ without TEX remapping, they are a table index. 136 * ARMv6+ with TEX remapping, they correspond to n/a,TEX(0),C,B 137 * 138 * MT type Pre-ARMv6 ARMv6+ type / cacheable status 139 * UNCACHED Uncached Strongly ordered 140 * BUFFERABLE Bufferable Normal memory / non-cacheable 141 * WRITETHROUGH Writethrough Normal memory / write through 142 * WRITEBACK Writeback Normal memory / write back, read alloc 143 * MINICACHE Minicache N/A 144 * WRITEALLOC Writeback Normal memory / write back, write alloc 145 * DEV_SHARED Uncached Device memory (shared) 146 * DEV_NONSHARED Uncached Device memory (non-shared) 147 * DEV_WC Bufferable Normal memory / non-cacheable 148 * DEV_CACHED Writeback Normal memory / write back, read alloc 149 * VECTORS Variable Normal memory / variable 150 * 151 * All normal memory mappings have the following properties: 152 * - reads can be repeated with no side effects 153 * - repeated reads return the last value written 154 * - reads can fetch additional locations without side effects 155 * - writes can be repeated (in certain cases) with no side effects 156 * - writes can be merged before accessing the target 157 * - unaligned accesses can be supported 158 * 159 * All device mappings have the following properties: 160 * - no access speculation 161 * - no repetition (eg, on return from an exception) 162 * - number, order and size of accesses are maintained 163 * - unaligned accesses are "unpredictable" 164 */ 165 #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */ 166 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ 167 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ 168 #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ 169 #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ 170 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ 171 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ 172 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ 173 #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ 174 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ 175 #define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */ 176 #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) 177 178 #ifndef __ASSEMBLY__ 179 180 /* 181 * The "pud_xxx()" functions here are trivial when the pmd is folded into 182 * the pud: the pud entry is never bad, always exists, and can't be set or 183 * cleared. 184 */ pud_none(pud_t pud)185 static inline int pud_none(pud_t pud) 186 { 187 return 0; 188 } 189 pud_bad(pud_t pud)190 static inline int pud_bad(pud_t pud) 191 { 192 return 0; 193 } 194 pud_present(pud_t pud)195 static inline int pud_present(pud_t pud) 196 { 197 return 1; 198 } 199 pud_clear(pud_t * pudp)200 static inline void pud_clear(pud_t *pudp) 201 { 202 } 203 set_pud(pud_t * pudp,pud_t pud)204 static inline void set_pud(pud_t *pudp, pud_t pud) 205 { 206 } 207 pmd_offset(pud_t * pud,unsigned long addr)208 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr) 209 { 210 return (pmd_t *)pud; 211 } 212 #define pmd_offset pmd_offset 213 214 #define pmd_pfn(pmd) (__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) 215 216 #define pmd_leaf(pmd) (pmd_val(pmd) & PMD_TYPE_SECT) 217 #define pmd_bad(pmd) pmd_leaf(pmd) 218 #define pmd_present(pmd) (pmd_val(pmd)) 219 220 #define copy_pmd(pmdpd,pmdps) \ 221 do { \ 222 pmdpd[0] = pmdps[0]; \ 223 pmdpd[1] = pmdps[1]; \ 224 flush_pmd_entry(pmdpd); \ 225 } while (0) 226 227 #define pmd_clear(pmdp) \ 228 do { \ 229 pmdp[0] = __pmd(0); \ 230 pmdp[1] = __pmd(0); \ 231 clean_pmd_entry(pmdp); \ 232 } while (0) 233 234 /* we don't need complex calculations here as the pmd is folded into the pgd */ 235 #define pmd_addr_end(addr,end) (end) 236 237 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) 238 239 /* 240 * We don't have huge page support for short descriptors, for the moment 241 * define empty stubs for use by pin_page_for_write. 242 */ 243 #define pmd_hugewillfault(pmd) (0) 244 245 #endif /* __ASSEMBLY__ */ 246 247 #endif /* _ASM_PGTABLE_2LEVEL_H */ 248