1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef __AMDGPU_REG_STATE_H__ 26 #define __AMDGPU_REG_STATE_H__ 27 28 enum amdgpu_reg_state { 29 AMDGPU_REG_STATE_TYPE_INVALID = 0, 30 AMDGPU_REG_STATE_TYPE_XGMI = 1, 31 AMDGPU_REG_STATE_TYPE_WAFL = 2, 32 AMDGPU_REG_STATE_TYPE_PCIE = 3, 33 AMDGPU_REG_STATE_TYPE_USR = 4, 34 AMDGPU_REG_STATE_TYPE_USR_1 = 5 35 }; 36 37 enum amdgpu_sysfs_reg_offset { 38 AMDGPU_SYS_REG_STATE_XGMI = 0x0000, 39 AMDGPU_SYS_REG_STATE_WAFL = 0x1000, 40 AMDGPU_SYS_REG_STATE_PCIE = 0x2000, 41 AMDGPU_SYS_REG_STATE_USR = 0x3000, 42 AMDGPU_SYS_REG_STATE_USR_1 = 0x4000, 43 AMDGPU_SYS_REG_STATE_END = 0x5000, 44 }; 45 46 struct amdgpu_reg_state_header { 47 uint16_t structure_size; 48 uint8_t format_revision; 49 uint8_t content_revision; 50 uint8_t state_type; 51 uint8_t num_instances; 52 uint16_t pad; 53 }; 54 55 enum amdgpu_reg_inst_state { 56 AMDGPU_INST_S_OK, 57 AMDGPU_INST_S_EDISABLED, 58 AMDGPU_INST_S_EACCESS, 59 }; 60 61 struct amdgpu_smn_reg_data { 62 uint64_t addr; 63 uint32_t value; 64 uint32_t pad; 65 }; 66 67 struct amdgpu_reg_inst_header { 68 uint16_t instance; 69 uint16_t state; 70 uint16_t num_smn_regs; 71 uint16_t pad; 72 }; 73 74 75 struct amdgpu_regs_xgmi_v1_0 { 76 struct amdgpu_reg_inst_header inst_header; 77 78 struct amdgpu_smn_reg_data smn_reg_values[]; 79 }; 80 81 struct amdgpu_reg_state_xgmi_v1_0 { 82 /* common_header.state_type must be AMDGPU_REG_STATE_TYPE_XGMI */ 83 struct amdgpu_reg_state_header common_header; 84 85 struct amdgpu_regs_xgmi_v1_0 xgmi_state_regs[]; 86 }; 87 88 struct amdgpu_regs_wafl_v1_0 { 89 struct amdgpu_reg_inst_header inst_header; 90 91 struct amdgpu_smn_reg_data smn_reg_values[]; 92 }; 93 94 struct amdgpu_reg_state_wafl_v1_0 { 95 /* common_header.state_type must be AMDGPU_REG_STATE_TYPE_WAFL */ 96 struct amdgpu_reg_state_header common_header; 97 98 struct amdgpu_regs_wafl_v1_0 wafl_state_regs[]; 99 }; 100 101 struct amdgpu_regs_pcie_v1_0 { 102 struct amdgpu_reg_inst_header inst_header; 103 104 uint16_t device_status; 105 uint16_t link_status; 106 uint32_t sub_bus_number_latency; 107 uint32_t pcie_corr_err_status; 108 uint32_t pcie_uncorr_err_status; 109 110 struct amdgpu_smn_reg_data smn_reg_values[]; 111 }; 112 113 struct amdgpu_reg_state_pcie_v1_0 { 114 /* common_header.state_type must be AMDGPU_REG_STATE_TYPE_PCIE */ 115 struct amdgpu_reg_state_header common_header; 116 117 struct amdgpu_regs_pcie_v1_0 pci_state_regs[]; 118 }; 119 120 struct amdgpu_regs_usr_v1_0 { 121 struct amdgpu_reg_inst_header inst_header; 122 123 struct amdgpu_smn_reg_data smn_reg_values[]; 124 }; 125 126 struct amdgpu_reg_state_usr_v1_0 { 127 /* common_header.state_type must be AMDGPU_REG_STATE_TYPE_USR */ 128 struct amdgpu_reg_state_header common_header; 129 130 struct amdgpu_regs_usr_v1_0 usr_state_regs[]; 131 }; 132 amdgpu_reginst_size(uint16_t num_inst,size_t inst_size,uint16_t num_regs)133 static inline size_t amdgpu_reginst_size(uint16_t num_inst, size_t inst_size, 134 uint16_t num_regs) 135 { 136 return num_inst * 137 (inst_size + num_regs * sizeof(struct amdgpu_smn_reg_data)); 138 } 139 140 #define amdgpu_asic_get_reg_state_supported(adev) \ 141 (((adev)->asic_funcs && (adev)->asic_funcs->get_reg_state) ? 1 : 0) 142 143 #define amdgpu_asic_get_reg_state(adev, state, buf, size) \ 144 ((adev)->asic_funcs->get_reg_state ? \ 145 (adev)->asic_funcs->get_reg_state((adev), (state), (buf), \ 146 (size)) : \ 147 0) 148 149 150 int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev); 151 void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev); 152 153 #endif 154