1.. SPDX-License-Identifier: GPL-2.0-only
2
3=============
4AD4695 driver
5=============
6
7ADC driver for Analog Devices Inc. AD4695 and similar devices. The module name
8is ``ad4695``.
9
10
11Supported devices
12=================
13
14The following chips are supported by this driver:
15
16* `AD4695 <https://www.analog.com/AD4695>`_
17* `AD4696 <https://www.analog.com/AD4696>`_
18* `AD4697 <https://www.analog.com/AD4697>`_
19* `AD4698 <https://www.analog.com/AD4698>`_
20
21
22Supported features
23==================
24
25SPI wiring modes
26----------------
27
28The driver currently supports the following SPI wiring configuration:
29
304-wire mode
31^^^^^^^^^^^
32
33In this mode, CNV and CS are tied together and there is a single SDO line.
34
35.. code-block::
36
37    +-------------+         +-------------+
38    |          CS |<-+------| CS          |
39    |         CNV |<-+      |             |
40    |     ADC     |         |     HOST    |
41    |             |         |             |
42    |         SDI |<--------| SDO         |
43    |         SDO |-------->| SDI         |
44    |        SCLK |<--------| SCLK        |
45    +-------------+         +-------------+
46
47To use this mode, in the device tree, omit the ``cnv-gpios`` and
48``spi-rx-bus-width`` properties.
49
50Channel configuration
51---------------------
52
53Since the chip supports multiple ways to configure each channel, this must be
54described in the device tree based on what is actually wired up to the inputs.
55
56There are three typical configurations:
57
58An ``INx`` pin is used as the positive input with the ``REFGND``, ``COM`` or
59the next ``INx`` pin as the negative input.
60
61Pairing with REFGND
62^^^^^^^^^^^^^^^^^^^
63
64Each ``INx`` pin can be used as a pseudo-differential input in conjunction with
65the ``REFGND`` pin. The device tree will look like this:
66
67.. code-block::
68
69    channel@0 {
70        reg = <0>; /* IN0 */
71    };
72
73If no other channel properties are needed (e.g. ``adi,no-high-z``), the channel
74node can be omitted entirely.
75
76This will appear on the IIO bus as the ``voltage0`` channel. The processed value
77(*raw × scale*) will be the voltage present on the ``IN0`` pin relative to
78``REFGND``. (Offset is always 0 when pairing with ``REFGND``.)
79
80Pairing with COM
81^^^^^^^^^^^^^^^^
82
83Each ``INx`` pin can be used as a pseudo-differential input in conjunction with
84the ``COM`` pin. The device tree will look like this:
85
86.. code-block::
87
88    com-supply = <&vref_div_2>;
89
90    channel@1 {
91        reg = <1>; /* IN1 */
92        common-mode-channel = <AD4695_COMMON_MODE_COM>;
93        bipolar;
94    };
95
96This will appear on the IIO bus as the ``voltage1`` channel. The processed value
97(*(raw + offset) × scale*) will be the voltage measured on the ``IN1`` pin
98relative to ``REFGND``. (The offset is determined by the ``com-supply`` voltage.)
99
100The macro comes from:
101
102.. code-block::
103
104    #include <dt-bindings/iio/adi,ad4695.h>
105
106Pairing two INx pins
107^^^^^^^^^^^^^^^^^^^^
108
109An even-numbered ``INx`` pin and the following odd-numbered ``INx`` pin can be
110used as a pseudo-differential input. The device tree for using ``IN2`` as the
111positive input and ``IN3`` as the negative input will look like this:
112
113.. code-block::
114
115    in3-supply = <&vref_div_2>;
116
117    channel@2 {
118        reg = <2>; /* IN2 */
119        common-mode-channel = <3>; /* IN3 */
120        bipolar;
121    };
122
123This will appear on the IIO bus as the ``voltage2`` channel. The processed value
124(*(raw + offset) × scale*) will be the voltage measured on the ``IN1`` pin
125relative to ``REFGND``. (Offset is determined by the ``in3-supply`` voltage.)
126
127VCC supply
128----------
129
130The chip supports being powered by an external LDO via the ``VCC`` input or an
131internal LDO via the ``LDO_IN`` input. The driver looks at the device tree to
132determine which is being used. If ``ldo-supply`` is present, then the internal
133LDO is used. If ``vcc-supply`` is present, then the external LDO is used and
134the internal LDO is disabled.
135
136Reference voltage
137-----------------
138
139The chip supports an external reference voltage via the ``REF`` input or an
140internal buffered reference voltage via the ``REFIN`` input. The driver looks
141at the device tree to determine which is being used. If ``ref-supply`` is
142present, then the external reference voltage is used and the internal buffer is
143disabled. If ``refin-supply`` is present, then the internal buffered reference
144voltage is used.
145
146Gain/offset calibration
147-----------------------
148
149System calibration is supported using the channel gain and offset registers via
150the ``calibscale`` and ``calibbias`` attributes respectively.
151
152Unimplemented features
153----------------------
154
155- Additional wiring modes
156- Threshold events
157- Oversampling
158- GPIO support
159- CRC support
160
161Device buffers
162==============
163
164This driver supports hardware triggered buffers. This uses the "advanced
165sequencer" feature of the chip to trigger a burst of conversions.
166
167Also see :doc:`iio_devbuf` for more general information.
168