1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2# Copyright 2019 Linaro Ltd.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: QCOM SoC Temperature Sensor (TSENS)
9
10maintainers:
11  - Amit Kucheria <amitk@kernel.org>
12
13description: |
14  QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
15  three distinct major versions of the IP that is supported by a single driver.
16  The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
17  everything before v1 when there was no versioning information.
18
19properties:
20  compatible:
21    oneOf:
22      - description: msm8960 TSENS based
23        items:
24          - enum:
25              - qcom,ipq8064-tsens
26              - qcom,msm8960-tsens
27
28      - description: v0.1 of TSENS
29        items:
30          - enum:
31              - qcom,mdm9607-tsens
32              - qcom,msm8226-tsens
33              - qcom,msm8909-tsens
34              - qcom,msm8916-tsens
35              - qcom,msm8939-tsens
36              - qcom,msm8974-tsens
37          - const: qcom,tsens-v0_1
38
39      - description: v1 of TSENS
40        items:
41          - enum:
42              - qcom,msm8956-tsens
43              - qcom,msm8976-tsens
44              - qcom,qcs404-tsens
45          - const: qcom,tsens-v1
46
47      - description: v2 of TSENS
48        items:
49          - enum:
50              - qcom,msm8953-tsens
51              - qcom,msm8996-tsens
52              - qcom,msm8998-tsens
53              - qcom,qcm2290-tsens
54              - qcom,sa8255p-tsens
55              - qcom,sa8775p-tsens
56              - qcom,sc7180-tsens
57              - qcom,sc7280-tsens
58              - qcom,sc8180x-tsens
59              - qcom,sc8280xp-tsens
60              - qcom,sdm630-tsens
61              - qcom,sdm845-tsens
62              - qcom,sm6115-tsens
63              - qcom,sm6350-tsens
64              - qcom,sm6375-tsens
65              - qcom,sm8150-tsens
66              - qcom,sm8250-tsens
67              - qcom,sm8350-tsens
68              - qcom,sm8450-tsens
69              - qcom,sm8550-tsens
70              - qcom,sm8650-tsens
71              - qcom,x1e80100-tsens
72          - const: qcom,tsens-v2
73
74      - description: v2 of TSENS with combined interrupt
75        enum:
76          - qcom,ipq8074-tsens
77
78      - description: v2 of TSENS with combined interrupt
79        items:
80          - enum:
81              - qcom,ipq9574-tsens
82          - const: qcom,ipq8074-tsens
83
84  reg:
85    items:
86      - description: TM registers
87      - description: SROT registers
88
89  interrupts:
90    minItems: 1
91    maxItems: 2
92
93  interrupt-names:
94    minItems: 1
95    maxItems: 2
96
97  nvmem-cells:
98    oneOf:
99      - minItems: 1
100        maxItems: 2
101        description:
102          Reference to an nvmem node for the calibration data
103      - minItems: 5
104        maxItems: 35
105        description: |
106          Reference to nvmem cells for the calibration mode, two calibration
107          bases and two cells per each sensor
108        # special case for msm8974 / apq8084
109      - maxItems: 51
110        description: |
111          Reference to nvmem cells for the calibration mode, two calibration
112          bases and two cells per each sensor, main and backup copies, plus use_backup cell
113
114  nvmem-cell-names:
115    oneOf:
116      - minItems: 1
117        items:
118          - const: calib
119          - enum:
120              - calib_backup
121              - calib_sel
122      - minItems: 5
123        items:
124          - const: mode
125          - const: base1
126          - const: base2
127          - pattern: '^s[0-9]+_p1$'
128          - pattern: '^s[0-9]+_p2$'
129          - pattern: '^s[0-9]+_p1$'
130          - pattern: '^s[0-9]+_p2$'
131          - pattern: '^s[0-9]+_p1$'
132          - pattern: '^s[0-9]+_p2$'
133          - pattern: '^s[0-9]+_p1$'
134          - pattern: '^s[0-9]+_p2$'
135          - pattern: '^s[0-9]+_p1$'
136          - pattern: '^s[0-9]+_p2$'
137          - pattern: '^s[0-9]+_p1$'
138          - pattern: '^s[0-9]+_p2$'
139          - pattern: '^s[0-9]+_p1$'
140          - pattern: '^s[0-9]+_p2$'
141          - pattern: '^s[0-9]+_p1$'
142          - pattern: '^s[0-9]+_p2$'
143          - pattern: '^s[0-9]+_p1$'
144          - pattern: '^s[0-9]+_p2$'
145          - pattern: '^s[0-9]+_p1$'
146          - pattern: '^s[0-9]+_p2$'
147          - pattern: '^s[0-9]+_p1$'
148          - pattern: '^s[0-9]+_p2$'
149          - pattern: '^s[0-9]+_p1$'
150          - pattern: '^s[0-9]+_p2$'
151          - pattern: '^s[0-9]+_p1$'
152          - pattern: '^s[0-9]+_p2$'
153          - pattern: '^s[0-9]+_p1$'
154          - pattern: '^s[0-9]+_p2$'
155          - pattern: '^s[0-9]+_p1$'
156          - pattern: '^s[0-9]+_p2$'
157          - pattern: '^s[0-9]+_p1$'
158          - pattern: '^s[0-9]+_p2$'
159        # special case for msm8974 / apq8084
160      - items:
161          - const: mode
162          - const: base1
163          - const: base2
164          - const: use_backup
165          - const: mode_backup
166          - const: base1_backup
167          - const: base2_backup
168          - const: s0_p1
169          - const: s0_p2
170          - const: s1_p1
171          - const: s1_p2
172          - const: s2_p1
173          - const: s2_p2
174          - const: s3_p1
175          - const: s3_p2
176          - const: s4_p1
177          - const: s4_p2
178          - const: s5_p1
179          - const: s5_p2
180          - const: s6_p1
181          - const: s6_p2
182          - const: s7_p1
183          - const: s7_p2
184          - const: s8_p1
185          - const: s8_p2
186          - const: s9_p1
187          - const: s9_p2
188          - const: s10_p1
189          - const: s10_p2
190          - const: s0_p1_backup
191          - const: s0_p2_backup
192          - const: s1_p1_backup
193          - const: s1_p2_backup
194          - const: s2_p1_backup
195          - const: s2_p2_backup
196          - const: s3_p1_backup
197          - const: s3_p2_backup
198          - const: s4_p1_backup
199          - const: s4_p2_backup
200          - const: s5_p1_backup
201          - const: s5_p2_backup
202          - const: s6_p1_backup
203          - const: s6_p2_backup
204          - const: s7_p1_backup
205          - const: s7_p2_backup
206          - const: s8_p1_backup
207          - const: s8_p2_backup
208          - const: s9_p1_backup
209          - const: s9_p2_backup
210          - const: s10_p1_backup
211          - const: s10_p2_backup
212
213  "#qcom,sensors":
214    description:
215      Number of sensors enabled on this platform
216    $ref: /schemas/types.yaml#/definitions/uint32
217    minimum: 1
218    maximum: 16
219
220  "#thermal-sensor-cells":
221    const: 1
222
223required:
224  - compatible
225  - interrupts
226  - interrupt-names
227  - "#qcom,sensors"
228
229allOf:
230  - $ref: thermal-sensor.yaml#
231
232  - if:
233      properties:
234        compatible:
235          contains:
236            enum:
237              - qcom,ipq8064-tsens
238              - qcom,msm8960-tsens
239              - qcom,tsens-v0_1
240              - qcom,tsens-v1
241    then:
242      properties:
243        interrupts:
244          items:
245            - description: Combined interrupt if upper or lower threshold crossed
246        interrupt-names:
247          items:
248            - const: uplow
249
250  - if:
251      properties:
252        compatible:
253          contains:
254            const: qcom,tsens-v2
255    then:
256      properties:
257        interrupts:
258          items:
259            - description: Combined interrupt if upper or lower threshold crossed
260            - description: Interrupt if critical threshold crossed
261        interrupt-names:
262          items:
263            - const: uplow
264            - const: critical
265
266  - if:
267      properties:
268        compatible:
269          contains:
270            enum:
271              - qcom,ipq8074-tsens
272    then:
273      properties:
274        interrupts:
275          items:
276            - description: Combined interrupt if upper, lower or critical thresholds crossed
277        interrupt-names:
278          items:
279            - const: combined
280
281  - if:
282      properties:
283        compatible:
284          contains:
285            enum:
286              - qcom,ipq8074-tsens
287              - qcom,tsens-v0_1
288              - qcom,tsens-v1
289              - qcom,tsens-v2
290
291    then:
292      required:
293        - reg
294
295unevaluatedProperties: false
296
297examples:
298  - |
299    #include <dt-bindings/interrupt-controller/arm-gic.h>
300    thermal-sensor {
301        compatible = "qcom,ipq8064-tsens";
302
303        nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
304        nvmem-cell-names = "calib", "calib_backup";
305        interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
306        interrupt-names = "uplow";
307
308        #qcom,sensors = <11>;
309        #thermal-sensor-cells = <1>;
310    };
311
312  - |
313    #include <dt-bindings/interrupt-controller/arm-gic.h>
314    // Example 1 (new calibration data: for pre v1 IP):
315    thermal-sensor@4a9000 {
316        compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
317        reg = <0x4a9000 0x1000>, /* TM */
318              <0x4a8000 0x1000>; /* SROT */
319
320        nvmem-cells = <&tsens_mode>,
321                      <&tsens_base1>, <&tsens_base2>,
322                      <&tsens_s0_p1>, <&tsens_s0_p2>,
323                      <&tsens_s1_p1>, <&tsens_s1_p2>,
324                      <&tsens_s2_p1>, <&tsens_s2_p2>,
325                      <&tsens_s4_p1>, <&tsens_s4_p2>,
326                      <&tsens_s5_p1>, <&tsens_s5_p2>;
327        nvmem-cell-names = "mode",
328                           "base1", "base2",
329                           "s0_p1", "s0_p2",
330                           "s1_p1", "s1_p2",
331                           "s2_p1", "s2_p2",
332                           "s4_p1", "s4_p2",
333                           "s5_p1", "s5_p2";
334
335        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
336        interrupt-names = "uplow";
337
338        #qcom,sensors = <5>;
339        #thermal-sensor-cells = <1>;
340    };
341
342  - |
343    #include <dt-bindings/interrupt-controller/arm-gic.h>
344    // Example 1 (legacy: for pre v1 IP):
345    tsens1: thermal-sensor@4a9000 {
346        compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
347        reg = <0x4a9000 0x1000>, /* TM */
348              <0x4a8000 0x1000>; /* SROT */
349
350        nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
351        nvmem-cell-names = "calib", "calib_sel";
352
353        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
354        interrupt-names = "uplow";
355
356        #qcom,sensors = <5>;
357        #thermal-sensor-cells = <1>;
358    };
359
360  - |
361    #include <dt-bindings/interrupt-controller/arm-gic.h>
362    // Example 2 (for any platform containing v1 of the TSENS IP):
363    tsens2: thermal-sensor@4a9000 {
364        compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
365        reg = <0x004a9000 0x1000>, /* TM */
366              <0x004a8000 0x1000>; /* SROT */
367
368        nvmem-cells = <&tsens_caldata>;
369        nvmem-cell-names = "calib";
370
371        interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
372        interrupt-names = "uplow";
373
374        #qcom,sensors = <10>;
375        #thermal-sensor-cells = <1>;
376    };
377
378  - |
379    #include <dt-bindings/interrupt-controller/arm-gic.h>
380    // Example 3 (for any platform containing v2 of the TSENS IP):
381    tsens3: thermal-sensor@c263000 {
382        compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
383        reg = <0xc263000 0x1ff>,
384              <0xc222000 0x1ff>;
385
386        interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
387                     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
388        interrupt-names = "uplow", "critical";
389
390        #qcom,sensors = <13>;
391        #thermal-sensor-cells = <1>;
392    };
393
394  - |
395    #include <dt-bindings/interrupt-controller/arm-gic.h>
396    // Example 4 (for any IPQ8074 based SoC-s):
397    tsens4: thermal-sensor@4a9000 {
398        compatible = "qcom,ipq8074-tsens";
399        reg = <0x4a9000 0x1000>,
400              <0x4a8000 0x1000>;
401
402        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
403        interrupt-names = "combined";
404
405        #qcom,sensors = <16>;
406        #thermal-sensor-cells = <1>;
407    };
408...
409