1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip designware mobile storage host controller 8 9description: 10 Rockchip uses the Synopsys designware mobile storage host controller 11 to interface a SoC with storage medium such as eMMC or SD/MMC cards. 12 This file documents the combined properties for the core Synopsys dw mshc 13 controller that are not already included in the synopsys-dw-mshc-common.yaml 14 file and the Rockchip specific extensions. 15 16allOf: 17 - $ref: synopsys-dw-mshc-common.yaml# 18 19maintainers: 20 - Heiko Stuebner <heiko@sntech.de> 21 22# Everything else is described in the common file 23properties: 24 compatible: 25 oneOf: 26 # for Rockchip RK2928 and before RK3288 27 - const: rockchip,rk2928-dw-mshc 28 # for Rockchip RK3288 29 - const: rockchip,rk3288-dw-mshc 30 - items: 31 - enum: 32 - rockchip,px30-dw-mshc 33 - rockchip,rk1808-dw-mshc 34 - rockchip,rk3036-dw-mshc 35 - rockchip,rk3128-dw-mshc 36 - rockchip,rk3228-dw-mshc 37 - rockchip,rk3308-dw-mshc 38 - rockchip,rk3328-dw-mshc 39 - rockchip,rk3368-dw-mshc 40 - rockchip,rk3399-dw-mshc 41 - rockchip,rk3568-dw-mshc 42 - rockchip,rk3588-dw-mshc 43 - rockchip,rv1108-dw-mshc 44 - rockchip,rv1126-dw-mshc 45 - const: rockchip,rk3288-dw-mshc 46 # for Rockchip RK3576 with phase tuning inside the controller 47 - const: rockchip,rk3576-dw-mshc 48 49 reg: 50 maxItems: 1 51 52 interrupts: 53 maxItems: 1 54 55 clocks: 56 minItems: 2 57 maxItems: 4 58 description: 59 Handle to "biu" and "ciu" clocks for the bus interface unit clock and 60 the card interface unit clock. If "ciu-drive" and "ciu-sample" are 61 specified in clock-names, it should also contain 62 handles to these clocks. 63 64 clock-names: 65 minItems: 2 66 items: 67 - const: biu 68 - const: ciu 69 - const: ciu-drive 70 - const: ciu-sample 71 description: 72 Apart from the clock-names "biu" and "ciu" two more clocks 73 "ciu-drive" and "ciu-sample" are supported. They are used 74 to control the clock phases, "ciu-sample" is required for tuning 75 high speed modes. 76 77 power-domains: 78 maxItems: 1 79 80 rockchip,default-sample-phase: 81 $ref: /schemas/types.yaml#/definitions/uint32 82 minimum: 0 83 maximum: 360 84 default: 0 85 description: 86 The default phase to set "ciu-sample" at probing, 87 low speeds or in case where all phases work at tuning time. 88 If not specified 0 deg will be used. 89 90 rockchip,desired-num-phases: 91 $ref: /schemas/types.yaml#/definitions/uint32 92 minimum: 0 93 maximum: 360 94 default: 360 95 description: 96 The desired number of times that the host execute tuning when needed. 97 If not specified, the host will do tuning for 360 times, 98 namely tuning for each degree. 99 100required: 101 - compatible 102 - reg 103 - interrupts 104 - clocks 105 - clock-names 106 107unevaluatedProperties: false 108 109examples: 110 - | 111 #include <dt-bindings/clock/rk3288-cru.h> 112 #include <dt-bindings/interrupt-controller/arm-gic.h> 113 #include <dt-bindings/interrupt-controller/irq.h> 114 sdmmc: mmc@ff0c0000 { 115 compatible = "rockchip,rk3288-dw-mshc"; 116 reg = <0xff0c0000 0x4000>; 117 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 119 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 120 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 121 resets = <&cru SRST_MMC0>; 122 reset-names = "reset"; 123 fifo-depth = <0x100>; 124 max-frequency = <150000000>; 125 }; 126 127... 128