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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dgpio-zynq.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq GPIO controller
10 - Michal Simek <michal.simek@amd.com>
15 - xlnx,zynq-gpio-1.0
16 - xlnx,zynqmp-gpio-1.0
17 - xlnx,versal-gpio-1.0
18 - xlnx,pmc-gpio-1.0
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/linux-6.12.1/drivers/gpio/
Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47 #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50 #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # GPIO infrastructure and drivers
7 bool "GPIO Support"
9 This enables GPIO support through the generic GPIO library.
11 one or more of the GPIO drivers below.
47 this symbol, but new drivers should use the generic gpio-regmap
51 bool "Debug GPIO calls"
54 Say Y here to add some extra checks and diagnostics to GPIO calls.
57 non-sleeping contexts. They can make bitbanged serial protocols
62 bool "/sys/class/gpio/... (sysfs interface)" if EXPERT
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/linux-6.12.1/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
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/linux-6.12.1/arch/arm/boot/dts/xilinx/
Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
28 stdout-path = "serial0:115200n8";
31 gpio-keys {
32 compatible = "gpio-keys";
34 switch-14 {
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Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
27 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
37 ps-clk-frequency = <33333333>;
42 phy-mode = "rgmii-id";
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/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dxlnx,pinctrl-zynq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 Zynq's pin configuration nodes act as a container for an arbitrary number of
21 parameters, such as pull-up, slew rate, etc.
31 const: xlnx,pinctrl-zynq
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/linux-6.12.1/Documentation/devicetree/bindings/fpga/
Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
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/linux-6.12.1/Documentation/devicetree/bindings/firmware/xilinx/
Dxlnx,zynqmp-firmware.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
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/linux-6.12.1/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
155 supports spi-mem interface.
231 With a few GPIO pins, your system can bitbang the SPI protocol.
232 Select this to get SPI support through I/O pins (GPIO, parallel
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Dspi-zynq-qspi.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
36 #define ZYNQ_QSPI_GPIO_OFFSET 0x30 /* GPIO Register, RW */
52 #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */
57 * QSPI Configuration Register - Baud rate and target select
109 #define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */
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Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
12 #include <linux/gpio/consumer.h>
25 #define CDNS_SPI_NAME "cdns-spi"
63 * SPI Configuration Register - Baud rate and target select
70 #define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
102 * struct cdns_spi - This definition defines spi driver instance
136 return readl_relaxed(xspi->regs + offset); in cdns_spi_read()
141 writel_relaxed(val, xspi->regs + offset); in cdns_spi_write()
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/linux-6.12.1/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
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/linux-6.12.1/drivers/mtd/nand/raw/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
126 include NAND flash controllers with built-in hardware ECC
161 - PXA3xx processors (NFCv1)
162 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
163 - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2)
229 Controller Module with built-in hardware ECC capabilities.
240 with built-in hardware ECC capabilities.
250 processor localbus with User-Programmable Machine support.
260 64 bytes or more of OOB, hardware ECC with up to 32-bit error
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/linux-6.12.1/drivers/tty/serial/
Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
25 #include <linux/gpio.h>
26 #include <linux/gpio/consumer.h>
42 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
47 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
90 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
96 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux-6.12.1/drivers/video/fbdev/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 a well-defined interface, so the software doesn't need to know
15 anything about the low-level (hardware register) stuff.
21 On several non-X86 architectures, the frame buffer device is the
29 and the Framebuffer-HOWTO at
30 <http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.3.html> for more
40 are compiling a kernel for a non-x86 architecture.
46 device-aware may cause unexpected results. If unsure, say N.
57 Common utility functions useful to fbdev drivers of VGA-based
82 If you have a PCI-based system, this enables support for these
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/linux-6.12.1/drivers/i2c/busses/
Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
37 #define CDNS_I2C_CR_MS BIT(1)
38 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */
40 /* 1 = Auto init FIFO to zeroes */
79 #define CDNS_I2C_IXR_DATA BIT(1)
121 #define CDNS_I2C_TRANSFER_SIZE(max) ((max) - 3)
123 #define DRIVER_NAME "cdns-i2c"
134 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
135 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
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/linux-6.12.1/drivers/iio/adc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
10 bool "ST-Ericsson AB8500 GPADC driver"
45 Say yes here to build support for Analog Devices AD4130-8 SPI analog
73 Say yes here to build support for Analog Devices AD7091R-5 ADC.
81 Say yes here to build support for Analog Devices AD7091R-2, AD7091R-4,
82 and AD7091R-8 ADC.
88 tristate "Analog Devices AD7124 and similar sigma-delta ADCs driver"
92 Say yes here to build support for Analog Devices AD7124-4 and AD7124-8
107 - AD7172-2
108 - AD7173-8
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/linux-6.12.1/drivers/net/ethernet/cadence/
Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
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/linux-6.12.1/drivers/watchdog/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 longer than 1 minute will result in rebooting the machine. This
16 on-line as fast as possible after a lock-up. There's both a watchdog
21 <file:Documentation/watchdog/watchdog-api.rst> in the kernel source.
51 bool "Update boot-enabled watchdog until userspace takes over"
77 bool "Enable watchdog hrtimer-based pretimeouts"
178 to toggle reset line if SoC fails to ping watchdog via GPIO.
198 tristate "ChromeOS EC-based watchdog"
252 tristate "Watchdog device controlled through GPIO-line"
257 controlled through GPIO-line.
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