Searched +full:xmem +full:- +full:adv +full:- +full:to +full:- +full:oe +full:- +full:recovery +full:- +full:cycles (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any11 external memory (such as NAND or other memory-mapped peripherals) whereas14 As it says it connects devices to an external bus interface, meaning address15 lines (up to 9 address lines so can only address 1KiB external memory space),16 data lines (16 bits), OE (output enable), ADV (address valid, used on some22 unused they can be left unconnected or remuxed to be used as GPIO or in some25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.[all …]
1 // SPDX-License-Identifier: GPL-2.0-only41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the42 * memory continues to drive the data bus after OE is de-asserted.43 * Inserted when reading one CS and switching to another CS or read45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first50 * write to a page or burst memory51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first52 * read to a page or burst memory53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle[all …]