| /linux-6.12.1/Documentation/filesystems/ |
| D | zonefs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ZoneFS - Zone filesystem for Zoned block devices
11 as a file. Unlike a regular POSIX-compliant file system with native zoned block
12 device support (e.g. f2fs), zonefs does not hide the sequential write
14 write zones of the device must be written sequentially starting from the end
15 of the file (append only writes).
18 than to a full-featured POSIX file system. The goal of zonefs is to simplify
22 example of this approach is the implementation of LSM (log-structured merge)
31 -------------------
38 conventional zones. Any read or write access can be executed, similarly to a
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| /linux-6.12.1/include/uapi/linux/ |
| D | virtio_mmio.h | 42 /* Magic value ("virt" string) - Read Only */
45 /* Virtio device version - Read Only */
48 /* Virtio device ID - Read Only */
51 /* Virtio vendor ID - Read Only */
55 * (32 bits per set) - Read Only */
58 /* Device (host) features set selector - Write Only */
62 * (32 bits per set) - Write Only */
65 /* Activated features set selector - Write Only */
69 #ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */
71 /* Guest's memory page size in bytes - Write Only */
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| D | virtio_pci.h | 46 /* A 32-bit r/o bitmask of the features supported by the host */
49 /* A 32-bit r/w bitmask of features activated by the guest */
52 /* A 32-bit r/w PFN for the currently selected queue */
55 /* A 16-bit r/o queue size for the currently selected queue */
58 /* A 16-bit r/w queue selector */
61 /* A 16-bit r/w queue notifier */
64 /* An 8-bit device status register. */
67 /* An 8-bit r/o interrupt status register. Reading the value will return the
69 * a read-and-acknowledge. */
72 /* MSI-X registers: only enabled if MSI-X is enabled. */
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-block-zram | 5 The disksize file is read-write and specifies the disk size
14 The initstate file is read-only and shows the initialization
21 The reset file is write-only and allows resetting the
29 The max_comp_streams file is read-write and specifies the
37 The comp_algorithm file is read-write and lets to show
45 The mem_used_max file is write-only and is used to reset
47 compressed data. For resetting the value, you should write
48 "0". Otherwise, you could see -EINVAL.
55 The mem_limit file is write-only and specifies the maximum
64 The compact file is write-only and trigger compaction for
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| D | sysfs-platform-dfl-fme | 1 What: /sys/bus/platform/devices/dfl-fme.0/ports_num
5 Description: Read-only. One DFL FPGA device may have more than 1
9 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_id
13 Description: Read-only. It returns Bitstream (static FPGA region)
17 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_metadata
21 Description: Read-only. It returns Bitstream (static FPGA region) meta
25 What: /sys/bus/platform/devices/dfl-fme.0/cache_size
29 Description: Read-only. It returns cache size of this FPGA device.
31 What: /sys/bus/platform/devices/dfl-fme.0/fabric_version
35 Description: Read-only. It returns fabric version of this FPGA device.
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| D | sysfs-platform-dfl-port | 1 What: /sys/bus/platform/devices/dfl-port.0/id
5 Description: Read-only. It returns id of this port. One DFL FPGA device
9 What: /sys/bus/platform/devices/dfl-port.0/afu_id
13 Description: Read-only. User can program different PR bitstreams to FPGA
18 What: /sys/bus/platform/devices/dfl-port.0/power_state
22 Description: Read-only. It reports the APx (AFU Power) state, different APx
24 returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
26 What: /sys/bus/platform/devices/dfl-port.0/ap1_event
30 Description: Read-write. Read this file for AP1 (AFU Power State 1) event.
31 It's used to indicate transient AP1 state. Write 1 to this
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| D | configfs-most | 7 Attributes are visible only when configfs is mounted. To mount
9 # mount -t configfs none /sys/kernel/config/
22 configure the sub-buffer size for this channel
40 for MediaLB communication only)
46 communication only)
58 write '1' to this attribute to trigger the
60 configuration, the creation is post-poned until
64 write '1' to this attribute to destroy an
77 configure the sub-buffer size for this channel
95 for MediaLB communication only)
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| D | sysfs-driver-qat_rl | 4 Contact: qat-linux@intel.com
10 this group before a write to this file.
34 This attribute is only available for qat_4xxx devices.
39 Contact: qat-linux@intel.com
45 The value is a 64-bit bit mask and is written/displayed in hex.
58 * WRITE: add operation
68 ## Write
71 This attribute is only available for qat_4xxx devices.
76 Contact: qat-linux@intel.com
80 This is valid only for the following operations: update, rm,
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| D | sysfs-class-firmware | 5 Description: The data sysfs file is used for firmware-fallback and for
8 image write is complete, echo 0 to the loading sysfs file. This
9 sequence will signal the completion of the firmware write and
10 signal the lower-level driver that the firmware data is
17 Description: Write-only. For firmware uploads, write a "1" to this file to
18 request that the transfer of firmware data to the lower-level
20 the update cannot be canceled (e.g. a FLASH write is in
27 Description: Read-only. Returns a string describing a failed firmware
31 following: "hw-error", "timeout", "user-abort", "device-busy",
32 "invalid-file-size", "read-write-error", "flash-wearout". The
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| /linux-6.12.1/Documentation/ABI/stable/ |
| D | sysfs-bus-nvmem | 6 This read/write attribute allows users to set read-write
7 devices as read-only and back to read-write from userspace.
8 This can be used to unlock and relock write-protection of
11 Read returns '0' or '1' for read-write or read-only modes
13 Write parses one of 'YyTt1NnFf0', or [oO][NnFf] for "on"
15 Note: This file is only present if CONFIG_NVMEM_SYSFS
23 This file allows user to read/write the raw NVMEM contents.
24 Permissions for write to this file depends on the nvmem
26 Note: This file is only present if CONFIG_NVMEM_SYSFS
46 This read-only attribute allows user to read the NVMEM
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| D | sysfs-driver-mlxreg-io | 1 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_health
6 0 - health failed, 2 - health OK, 3 - ASIC in booting state.
8 The files are read only.
10 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version
11 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version
18 The files are read only.
20 What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/fan_dir
25 forward direction - relevant bit is set 0;
26 reversed direction - relevant bit is set 1.
28 The files are read only.
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| /linux-6.12.1/fs/nls/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
23 default "iso8859-1"
31 cp949, cp950, cp1251, cp1255, euc-jp, euc-kr, gb2312, iso8859-1,
32 iso8859-2, iso8859-3, iso8859-4, iso8859-5, iso8859-6, iso8859-7,
33 iso8859-8, iso8859-9, iso8859-13, iso8859-14, iso8859-15,
34 koi8-r, koi8-ru, koi8-u, sjis, tis-620, macroman, utf8.
35 If you specify a wrong value, it will use the built-in NLS;
36 compatible with iso8859-1.
38 If unsure, specify it as "iso8859-1".
45 in so-called DOS codepages. You need to include the appropriate
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| /linux-6.12.1/tools/testing/selftests/kvm/x86_64/ |
| D | hyperv_features.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Tests for Hyper-V features enablement
18 * but to activate the feature it is sufficient to set it to a non-zero
27 bool write; member
47 GUEST_ASSERT(msr->idx); in guest_msr()
49 if (msr->write) in guest_msr()
50 vector = wrmsr_safe(msr->idx, msr->write_val); in guest_msr()
52 if (!vector && (!msr->write || !is_write_only_msr(msr->idx))) in guest_msr()
53 vector = rdmsr_safe(msr->idx, &msr_val); in guest_msr()
55 if (msr->fault_expected) in guest_msr()
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| /linux-6.12.1/Documentation/filesystems/spufs/ |
| D | spufs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 spufs - the SPU file system
21 message queues. Users that have write permissions on the file system
26 logical SPU. Users can change permissions on those files, but not actu-
43 The files in spufs mostly follow the standard behavior for regular sys-
44 tem calls like read(2) or write(2), but often support only a subset of
50 all files that support the write(2) operation also support writev(2).
52 only the st_mode, st_nlink, st_uid and st_gid fields of struct stat
55 All files support the chmod(2)/fchmod(2) and chown(2)/fchown(2) opera-
68 read(2), pread(2), write(2), pwrite(2), lseek(2)
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| /linux-6.12.1/sound/firewire/dice/ |
| D | dice-interface.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * block read transactions with at least quadlet-aligned offset and length.
12 * Writes are not allowed except where noted; quadlet-sized registers must be
13 * written with a quadlet write transaction.
15 * All values are in big endian. The DICE firmware runs on a little-endian CPU
16 * and just byte-swaps _all_ quadlets on the bus, so values without endianness
17 * (e.g. strings) get scrambled and must be byte-swapped again by the driver.
32 * size values are measured in quadlets. Read-only.
50 * Stores the full 64-bit address (node ID and offset in the node's address
60 * A bitmask with asynchronous events; read-only. When any event(s) happen,
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| /linux-6.12.1/include/soc/at91/ |
| D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
45 #define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
47 #define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
48 …ne AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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| /linux-6.12.1/include/linux/mfd/ |
| D | janz.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 * Write access: interrupt disable
29 * Write access: interrupt enable
34 /* write-only */
38 /* write-only */
42 /* read-write access to serial EEPROM */
46 /* write-only access to EEPROM chip select */
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | uncore-memory.json | 12 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
30 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
57 …"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read…
66 …tion": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
79 "PublicDescription": "Uncore Fixed Counter - uclks",
117 …rrors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRA…
126 …ected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or di…
136 …ected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or di…
146 …ected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or di…
151 "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
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| /linux-6.12.1/drivers/net/ethernet/ti/ |
| D | davinci_cpdma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
102 CPDMA_TX_RLIM, /* read-write */
103 CPDMA_CMD_IDLE, /* write-only */
104 CPDMA_COPY_ERROR_FRAMES, /* read-write */
105 CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
106 CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
107 CPDMA_TX_PRIO_FIXED, /* read-write */
108 CPDMA_STAT_IDLE, /* read-only */
109 CPDMA_STAT_TX_ERR_CHAN, /* read-only */
110 CPDMA_STAT_TX_ERR_CODE, /* read-only */
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| /linux-6.12.1/drivers/mtd/spi-nor/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
28 prompt "Software write protection at boot"
34 This option disables the software write protection on any SPI
35 flashes at boot-up.
40 Don't use this if you intent to use the software write protection
41 of your SPI flash. This is only to keep backwards compatibility.
47 power-up or a reset the flash is software write protected by
50 This option disables the software write protection for these kind
52 which have non-volatile write protection bits.
54 If the software write protection will be disabled depending on
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| /linux-6.12.1/Documentation/admin-guide/ |
| D | md.rst | 5 ---------------------------------
49 -1 linear mode
53 other modes are only supported with persistent super blocks
58 (raid-0 and raid-1 only)
78 --------------------------------------
83 ``raid=noautodetect``. As of kernel 2.6.9, only drives with a type 0
87 that all auto-detected arrays are assembled as partitionable.
90 -------------------------------------------
102 mdadm --assemble --force ....
112 md-mod.start_dirty_degraded=1
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| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| D | l1d_cache.json | 4 …oad or store operations that missed in the level 1 data cache. This event only counts one event pe…
8 …write access and read access. Each access to a cache line is counted including the multiple access…
12 …write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty …
16 …. Atomic load operations that resolve in the CPUs caches counts as both a write access and read ac…
20 …uction. Near atomic operations that resolve in the CPUs caches count as a write access and read ac…
24 …re the memory read operation misses in the level 1 data cache. This event only counts one event pe…
28 …xecuted store instructions where the memory write operation misses in the level 1 data cache. This…
44 …"PublicDescription": "Counts write-backs from the level 1 data cache that are a result of a cohere…
48 …n the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO) that operate by a virt…
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| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| D | l1d_cache.json | 4 …oad or store operations that missed in the level 1 data cache. This event only counts one event pe…
8 …write access and read access. Each access to a cache line is counted including the multiple access…
12 …write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty …
20 …. Atomic load operations that resolve in the CPUs caches counts as both a write access and read ac…
24 …uction. Near atomic operations that resolve in the CPUs caches count as a write access and read ac…
28 …re the memory read operation misses in the level 1 data cache. This event only counts one event pe…
32 …xecuted store instructions where the memory write operation misses in the level 1 data cache. This…
48 …"PublicDescription": "Counts write-backs from the level 1 data cache that are a result of a cohere…
52 …n the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO) that operate by a virt…
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| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| D | l1d_cache.json | 4 …oad or store operations that missed in the level 1 data cache. This event only counts one event pe…
8 …write access and read access. Each access to a cache line is counted including the multiple access…
12 …write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty …
20 …n. Atomic load operations that resolve in the CPUs caches count as both a write access and read ac…
24 …uction. Near atomic operations that resolve in the CPUs caches count as a write access and read ac…
28 …re the memory read operation misses in the level 1 data cache. This event only counts one event pe…
32 …xecuted store instructions where the memory write operation misses in the level 1 data cache. This…
48 …"PublicDescription": "Counts write-backs from the level 1 data cache that are a result of a cohere…
52 …n the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO) that operate by a virt…
|