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/linux-6.12.1/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mt7986-wed-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek PCIE WED Controller for MT7986
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
14 The mediatek WED PCIE provides a configuration interface for PCIE
20 - enum:
21 - mediatek,mt7986-wed-pcie
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Dmediatek,mt7622-wed.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
15 intercept and handle access to the WLAN DMA queues and PCIe interrupts
21 - enum:
22 - mediatek,mt7622-wed
23 - mediatek,mt7981-wed
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmediatek,net.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7621-eth
23 - mediatek,mt7622-eth
24 - mediatek,mt7629-eth
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt7986a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mt7986-clk.h>
10 #include <dt-bindings/reset/mt7986-resets.h>
11 #include <dt-bindings/phy/phy.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
[all …]
Dmt7622.dtsi6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7996/
Dmmio.c1 // SPDX-License-Identifier: ISC
95 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */
143 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, in mt7996_reg_map_l1()
147 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); in mt7996_reg_map_l1()
157 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, in mt7996_reg_map_l2()
161 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); in mt7996_reg_map_l2()
173 for (i = 0; i < dev->reg.map_size; i++) { in __mt7996_reg_addr()
176 if (addr < dev->reg.map[i].phys) in __mt7996_reg_addr()
179 ofs = addr - dev->reg.map[i].phys; in __mt7996_reg_addr()
180 if (ofs > dev->reg.map[i].size) in __mt7996_reg_addr()
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Dpci.c1 // SPDX-License-Identifier: ISC
38 val = readl(hif->regs + MT_PCIE_RECOG_ID); in mt7996_pci_get_hif2()
43 get_device(hif->dev); in mt7996_pci_get_hif2()
59 put_device(hif->dev); in mt7996_put_hif2()
80 hif = devm_kzalloc(&pdev->dev, sizeof(*hif), GFP_KERNEL); in mt7996_pci_hif2_probe()
82 return -ENOMEM; in mt7996_pci_hif2_probe()
84 hif->dev = &pdev->dev; in mt7996_pci_hif2_probe()
85 hif->regs = pcim_iomap_table(pdev)[0]; in mt7996_pci_hif2_probe()
86 hif->irq = pdev->irq; in mt7996_pci_hif2_probe()
88 list_add(&hif->list, &hif_list); in mt7996_pci_hif2_probe()
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/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7915/
Dpci.c1 // SPDX-License-Identifier: ISC
39 val = readl(hif->regs + MT_PCIE_RECOG_ID); in mt7915_pci_get_hif2()
44 get_device(hif->dev); in mt7915_pci_get_hif2()
60 put_device(hif->dev); in mt7915_put_hif2()
87 hif = devm_kzalloc(&pdev->dev, sizeof(*hif), GFP_KERNEL); in mt7915_pci_hif2_probe()
89 return -ENOMEM; in mt7915_pci_hif2_probe()
91 hif->dev = &pdev->dev; in mt7915_pci_hif2_probe()
92 hif->regs = pcim_iomap_table(pdev)[0]; in mt7915_pci_hif2_probe()
93 hif->irq = pdev->irq; in mt7915_pci_hif2_probe()
95 list_add(&hif->list, &hif_list); in mt7915_pci_hif2_probe()
[all …]
/linux-6.12.1/Documentation/arch/powerpc/
Dcxl.rst28 +----------+ +---------+
34 +----------+ +---------+
36 | +------+ | PSL |
37 | | CAPP |<------>| |
38 +---+------+ PCIE +---------+
41 unit which is part of the PCIe Host Bridge (PHB). This is managed
65 - POWER8 and PSL Version 8 are compliant to the CAIA Version 1.0.
66 - POWER9 and PSL Version 9 are compliant to the CAIA Version 2.0.
120 Work Element Descriptor (WED)
123 The WED is a 64-bit parameter passed to the AFU when a context is
[all …]
/linux-6.12.1/drivers/net/ethernet/mediatek/
Dmtk_wed.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
95 regmap_update_bits(dev->hw->regs, reg, mask | val, val); in wed_m32()
131 return readl(dev->wlan.base + reg); in wifi_r32()
137 writel(val, dev->wlan.base + reg); in wifi_w32()
157 if (!mtk_wed_is_v3_or_greater(dev->hw)) in mtk_wdma_v3_rx_reset()
166 dev_err(dev->hw->dev, "rx reset failed\n"); in mtk_wdma_v3_rx_reset()
171 dev_err(dev->hw->dev, "rx reset failed\n"); in mtk_wdma_v3_rx_reset()
179 dev_err(dev->hw->dev, "rx reset failed\n"); in mtk_wdma_v3_rx_reset()
184 dev_err(dev->hw->dev, "rx reset failed\n"); in mtk_wdma_v3_rx_reset()
[all …]
/linux-6.12.1/drivers/misc/cxl/
Dcxl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #include <misc/cxl-base.h>
64 /* Configuration and Control area - CAIA 1&2 */
74 /* PSL Lookaside Buffer Management Area - CAIA 1 */
83 /* PSL registers - CAIA 1 */
94 /* PSL registers - CAIA 2 */
116 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
117 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
120 /* Configuration Area - CAIA 1&2 */
127 /* Memory Management and Lookaside Buffer Management - CAIA 1*/
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
42 (clk_src->regs->reg)
45 clk_src->base.ctx
48 calc_pll_cs->ctx->logger
50 struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll
54 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
76 ss_parm = clk_src->dvi_ss_params; in get_ss_data_entry()
77 entrys_num = clk_src->dvi_ss_params_cnt; in get_ss_data_entry()
81 ss_parm = clk_src->hdmi_ss_params; in get_ss_data_entry()
82 entrys_num = clk_src->hdmi_ss_params_cnt; in get_ss_data_entry()
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