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/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
16 the timeout interval, an interrupt is generated and the WDT state
19 expiration of the timeout interval, a WDT reset is generated.
[all …]
/linux-6.12.1/drivers/watchdog/
Dof_xilinx_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2013 - 2014 Xilinx, Inc.
21 /* Register offsets for the Wdt device */
54 ret = clk_enable(xdev->clk); in xilinx_wdt_start()
56 dev_err(wdd->parent, "Failed to enable clock\n"); in xilinx_wdt_start()
60 spin_lock(&xdev->spinlock); in xilinx_wdt_start()
63 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()
67 xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()
69 iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); in xilinx_wdt_start()
71 spin_unlock(&xdev->spinlock); in xilinx_wdt_start()
[all …]
Drzn1_wdt.c1 // SPDX-License-Identifier: GPL-2.0
4 * This is a 12-bit timer driver from a (62.5/16384) MHz clock. It can't even
53 struct rzn1_watchdog *wdt = watchdog_get_drvdata(w); in rzn1_wdt_ping() local
56 writel(0, wdt->base + RZN1_WDT_RETRIGGER); in rzn1_wdt_ping()
63 struct rzn1_watchdog *wdt = watchdog_get_drvdata(w); in rzn1_wdt_start() local
69 * timeout once started. Also note that the WDT clock is half the bus in rzn1_wdt_start()
71 * the WDT is started, the WDT interval will be wrong. in rzn1_wdt_start()
76 val |= compute_reload_value(w->max_hw_heartbeat_ms, wdt->clk_rate_khz); in rzn1_wdt_start()
77 writel(val, wdt->base + RZN1_WDT_RETRIGGER); in rzn1_wdt_start()
103 struct device *dev = &pdev->dev; in rzn1_wdt_probe()
[all …]
Dnpcm_wdt.c1 // SPDX-License-Identifier: GPL-2.0
21 #define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */
57 struct npcm_wdt *wdt = to_npcm_wdt(wdd); in npcm_wdt_ping() local
60 val = readl(wdt->reg); in npcm_wdt_ping()
61 writel(val | NPCM_WTR, wdt->reg); in npcm_wdt_ping()
68 struct npcm_wdt *wdt = to_npcm_wdt(wdd); in npcm_wdt_start() local
71 if (wdt->clk) in npcm_wdt_start()
72 clk_prepare_enable(wdt->clk); in npcm_wdt_start()
74 if (wdd->timeout < 2) in npcm_wdt_start()
76 else if (wdd->timeout < 3) in npcm_wdt_start()
[all …]
Dshwdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
9 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
12 * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
35 #define DRV_NAME "sh-wdt"
39 * values, consult the asm-sh/watchdog.h. Overload this at module load
43 * something quite higher than 100 (or we need a proper high-res timer
46 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
47 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
57 * HZ == 1000), and another for monitoring userspace writes to the WDT device.
[all …]
Dsunxi_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 #define DRV_NAME "sunxi-wdt"
60 * wdt_timeout_map maps the watchdog timer interval value in seconds to
86 void __iomem *wdt_base = sunxi_wdt->wdt_base; in sunxi_wdt_restart()
87 const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs; in sunxi_wdt_restart()
91 val = readl(wdt_base + regs->wdt_cfg); in sunxi_wdt_restart()
92 val &= ~(regs->wdt_reset_mask); in sunxi_wdt_restart()
93 val |= regs->wdt_reset_val; in sunxi_wdt_restart()
94 val |= regs->wdt_key_val; in sunxi_wdt_restart()
95 writel(val, wdt_base + regs->wdt_cfg); in sunxi_wdt_restart()
[all …]
Dsbc60xxwdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * any of this software. This material is provided "AS-IS" in
13 * 12/4 - 2000 [Initial revision]
14 * 25/4 - 2000 Added /dev/watchdog support
15 * 09/5 - 2001 [smj@oro.net] fixed fop_write to "return 1"
17 * 12/4 - 2002 [rob@osinvestor.com] eliminate fop_read
28 * 09/8 - 2003 [wim@iguana.be] cleanup of trailing spaces
37 * This WDT driver is different from the other Linux WDT
40 * particular WDT has a very short timeout (one second) and it
67 * You must set these - The driver cannot probe for the settings
[all …]
Dw83877f_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * any of this software. This material is provided "AS-IS" in
14 * 4/19 - 2001 [Initial revision]
15 * 9/27 - 2001 Added spinlocking
16 * 4/12 - 2002 [rob@osinvestor.com] Eliminate extra comments
27 * 09/8 - 2003 [wim@iguana.be] cleanup of trailing spaces
34 * This WDT driver is different from most other Linux WDT
36 * because this particular WDT has a very short timeout (1.6
70 * EMACS PC-104 board I'm using). If we reset the watchdog every
110 * we agree to ping the WDT in wdt_timer_ping()
[all …]
Dalim7101_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * and the Cobalt kernel WDT timer driver by Tim Hockin
11 * This WDT driver is different from most other Linux WDT
13 * because this particular WDT has a very short timeout (1.6
18 * Aug 23, 2004 - Added use_gpio module parameter for use on revision a1d PMUs
20 * -- Mike Waychison <michael.waychison@sun.com>
94 * we agree to ping the WDT in wdt_timer_ping()
99 /* Ping the WDT (this is actually a disarm/arm sequence) */ in wdt_timer_ping()
116 /* Re-set the timer interval */ in wdt_timer_ping()
200 return -EFAULT; in fop_write()
[all …]
Dep93xx_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
15 * This watchdog fires after 250msec, which is a too short interval
17 * wdt each ~200msec and eventually stop doing it if the user space
49 writel(0xaaaa, priv->mmio + EP93XX_WATCHDOG); in ep93xx_wdt_start()
58 writel(0xaa55, priv->mmio + EP93XX_WATCHDOG); in ep93xx_wdt_stop()
67 writel(0x5555, priv->mmio + EP93XX_WATCHDOG); in ep93xx_wdt_ping()
89 struct device *dev = &pdev->dev; in ep93xx_wdt_probe()
97 return -ENOMEM; in ep93xx_wdt_probe()
99 priv->mmio = devm_platform_ioremap_resource(pdev, 0); in ep93xx_wdt_probe()
100 if (IS_ERR(priv->mmio)) in ep93xx_wdt_probe()
[all …]
Dsc520_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * any of this software. This material is provided "AS-IS" in
13 * 9/27 - 2001 [Initial release]
16 * - Fixed formatting
17 * - Removed debug printks
18 * - Fixed SMP built kernel deadlock
19 * - Switched to private locks not lock_kernel
20 * - Used ioremap/writew/readw
21 * - Added NOWAYOUT support
22 * 4/12 - 2002 Changes by Rob Radez <rob@osinvestor.com>
[all …]
Dgeodewdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2006-2007, Advanced Micro Devices, Inc.
30 #define WATCHDOG_NAME "Geode GX/LX WDT"
71 return -EINVAL; in geodewdt_set_heartbeat()
85 return -EBUSY; in geodewdt_open()
100 pr_crit("Unexpected close - watchdog is not stopping\n"); in geodewdt_release()
123 return -EFAULT; in geodewdt_write()
140 int interval; in geodewdt_ioctl() local
152 sizeof(ident)) ? -EFAULT : 0; in geodewdt_ioctl()
159 int options, ret = -EINVAL; in geodewdt_ioctl()
[all …]
Dat91rm9200_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <linux/mfd/syscon/atmel-st.h>
109 return -EBUSY; in at91_wdt_open()
131 * Change the watchdog time interval.
138 * Since WDV is a 16-bit counter, the maximum period is in at91_wdt_settimeout()
142 return -EINVAL; in at91_wdt_settimeout()
156 * Handle commands from user-space.
168 sizeof(at91_wdt_info)) ? -EFAULT : 0; in at91_wdt_ioctl()
174 return -EFAULT; in at91_wdt_ioctl()
185 return -EFAULT; in at91_wdt_ioctl()
[all …]
/linux-6.12.1/Documentation/ABI/stable/
Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
[all …]
/linux-6.12.1/arch/arm/boot/dts/rockchip/
Drk3066a-bqcurie2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
25 vdd_log: vdd-log {
26 compatible = "pwm-regulator";
28 regulator-name = "vdd_log";
29 regulator-min-microvolt = <1200000>;
30 regulator-max-microvolt = <1200000>;
31 regulator-always-on;
[all …]
Drk3066a-mk808.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
20 stdout-path = "serial2:115200n8";
28 adc-keys {
29 compatible = "adc-keys";
30 io-channels = <&saradc 1>;
31 io-channel-names = "buttons";
32 keyup-threshold-microvolt = <2500000>;
33 poll-interval = <100>;
[all …]
Drk3188-px3-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Andy Yan <andy.yan@rock-chips.com>
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
11 model = "Rockchip PX3-EVB";
12 compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
20 stdout-path = "serial2:115200n8";
28 gpio-keys {
29 compatible = "gpio-keys";
32 key-power {
[all …]
Drk3188-radxarock.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
23 gpio-keys {
24 compatible = "gpio-keys";
27 key-power {
31 linux,input-type = <1>;
32 wakeup-source;
33 debounce-interval = <100>;
37 gpio-leds {
[all …]
Drk3288-r89.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/pwm/pwm.h>
20 ext_gmac: external-gmac-clock {
21 compatible = "fixed-clock";
22 clock-frequency = <125000000>;
23 clock-output-names = "ext_gmac";
24 #clock-cells = <0>;
27 gpio-keys {
[all …]
Drk3288-evb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/pwm/pwm.h>
13 adc-keys {
14 compatible = "adc-keys";
15 io-channels = <&saradc 1>;
16 io-channel-names = "buttons";
17 keyup-threshold-microvolt = <1800000>;
19 button-up {
22 press-threshold-microvolt = <100000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dspear320-hmi.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear320-hmi", "st,spear320";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 st,pinmux-mode = <4>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&state_default>;
107 label = "u-boot";
129 compatible = "gpio-keys";
[all …]
Dspear1310-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear1310-evb", "st,spear1310";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
63 smi-pmx {
127 label = "u-boot";
149 compatible = "gpio-keys";
[all …]
Dspear1340-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 compatible = "st,spear1340-evb", "st,spear1340";
14 #address-cells = <1>;
15 #size-cells = <1>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>;
47 spdif-in {
51 spdif-out {
59 smi-pmx {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
33 compatible = "gpio-keys";
35 power-button {
[all …]
/linux-6.12.1/sound/soc/sof/mediatek/mt8195/
Dmt8195.h1 /* SPDX-License-Identifier: GPL-2.0 */
114 /* dsp wdt */
153 #define DRAM_REMAP_MASK (BIT(DRAM_REMAP_SHIFT) - 1)
155 /* suspend dsp idle check interval and timeout */

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