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/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
16 the timeout interval, an interrupt is generated and the WDT state
19 expiration of the timeout interval, a WDT reset is generated.
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/linux-6.12.1/drivers/watchdog/
Dimx2_wdt.c1 // SPDX-License-Identifier: GPL-2.0
14 * ---- -----
15 * Registers: 32-bit 16-bit
17 * Need to enable clk: No Yes
34 #define DRIVER_NAME "imx2-wdt"
37 #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38 #define IMX2_WDT_WCR_WDW BIT(7) /* -> Watchdog disable for WAIT */
39 #define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
40 #define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
41 #define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
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Dof_xilinx_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2013 - 2014 Xilinx, Inc.
21 /* Register offsets for the Wdt device */
29 #define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */
32 #define XWT_CSRX_EWDT2_MASK BIT(0) /* Enable bit 2 */
54 ret = clk_enable(xdev->clk); in xilinx_wdt_start()
56 dev_err(wdd->parent, "Failed to enable clock\n"); in xilinx_wdt_start()
60 spin_lock(&xdev->spinlock); in xilinx_wdt_start()
62 /* Clean previous status and enable the watchdog timer */ in xilinx_wdt_start()
63 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()
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Drn5t618_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #define DRIVER_NAME "rn5t618-wdt"
23 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
50 struct rn5t618_wdt *wdt = watchdog_get_drvdata(wdt_dev); in rn5t618_wdt_set_timeout() local
59 return -EINVAL; in rn5t618_wdt_set_timeout()
61 ret = regmap_update_bits(wdt->rn5t618->regmap, RN5T618_WATCHDOG, in rn5t618_wdt_set_timeout()
65 wdt_dev->timeout = rn5t618_wdt_map[i].time; in rn5t618_wdt_set_timeout()
72 struct rn5t618_wdt *wdt = watchdog_get_drvdata(wdt_dev); in rn5t618_wdt_start() local
75 ret = rn5t618_wdt_set_timeout(wdt_dev, wdt_dev->timeout); in rn5t618_wdt_start()
79 /* enable repower-on */ in rn5t618_wdt_start()
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Dlantiq_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
6 * Based on EP93xx wdt driver
33 * The password sequence protects the WDT control register from unintended
34 * write actions, which might cause malfunction of the WDT.
37 * IO access to the WDT core
43 #define LTQ_WDT_CR_GEN BIT(31) /* enable bit */
44 /* Pre-warning limit set to 1/16 of max WDT period */
49 #define LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
51 #define LTQ_WDT_SR_EN BIT(31) /* Enable */
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Dimx7ulp_wdt.c1 // SPDX-License-Identifier: GPL-2.0
53 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
78 return -ETIMEDOUT; in imx7ulp_wdt_wait_ulk()
83 static int imx7ulp_wdt_wait_rcs(struct imx7ulp_wdt_device *wdt) in imx7ulp_wdt_wait_rcs() argument
86 u32 val = readl(wdt->base + WDOG_CS); in imx7ulp_wdt_wait_rcs()
93 readl_poll_timeout(wdt->base + WDOG_CS, val, val & WDOG_CS_RCS, 100, in imx7ulp_wdt_wait_rcs()
95 ret = -ETIMEDOUT; in imx7ulp_wdt_wait_rcs()
98 if (wdt->hw->post_rcs_wait) in imx7ulp_wdt_wait_rcs()
104 static int _imx7ulp_wdt_enable(struct imx7ulp_wdt_device *wdt, bool enable) in _imx7ulp_wdt_enable() argument
106 u32 val = readl(wdt->base + WDOG_CS); in _imx7ulp_wdt_enable()
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Dmpc8xxx_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
12 * Note: it appears that you can only actually ENABLE or DISABLE the thing
13 * once after POR. Once enabled, you cannot disable, and vice versa.
34 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
69 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
74 /* Ping the WDT */ in mpc8xxx_wdt_keepalive()
75 spin_lock(&ddata->lock); in mpc8xxx_wdt_keepalive()
76 out_be16(&ddata->base->swsrr, 0x556c); in mpc8xxx_wdt_keepalive()
77 out_be16(&ddata->base->swsrr, 0xaa39); in mpc8xxx_wdt_keepalive()
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Dmax77620_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * struct max77620_variant - Data specific to a chip variant
34 * @cnfg_glbl2_cfg_bits: configuration bits to enable in CNFG_GLBL2 register
58 /* Set WDT clear in OFF and sleep mode */
68 /* Set WDT clear in sleep mode (there is no WDTOFFC on MAX77714) */
74 struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev); in max77620_wdt_start() local
76 return regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2, in max77620_wdt_start()
82 struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev); in max77620_wdt_stop() local
84 return regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2, in max77620_wdt_stop()
90 struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev); in max77620_wdt_ping() local
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Dstarfive-wdt.c1 // SPDX-License-Identifier: GPL-2.0
35 * [0]: reset enable;
36 * [1]: interrupt enable && watchdog enable
79 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
83 unsigned int control; /* Watchdog Control Resgister for reset enable */
86 unsigned int enable; /* Watchdog Enable Register */ member
117 .enable = STARFIVE_WDT_JH7100_EN,
134 .enable = STARFIVE_WDT_JH7110_CONTROL,
146 static int starfive_wdt_enable_clock(struct starfive_wdt *wdt) in starfive_wdt_enable_clock() argument
150 ret = clk_prepare_enable(wdt->apb_clk); in starfive_wdt_enable_clock()
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Dcadence_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence WDT driver - Used by Xilinx Zynq
5 * Copyright (C) 2010 - 2014 Xilinx, Inc.
21 /* Supports 1 - 516 sec */
59 "Watchdog cannot be stopped once started (default="
63 * struct cdns_wdt - Watchdog device structure
85 static inline void cdns_wdt_writereg(struct cdns_wdt *wdt, u32 offset, u32 val) in cdns_wdt_writereg() argument
87 writel_relaxed(val, wdt->regs + offset); in cdns_wdt_writereg()
92 /* Register Offsets for the WDT */
99 * Zero Mode Register - This register controls how the time out is indicated
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Dsmsc37b787_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * any of this software. This material is provided "AS-IS" in
12 * (C) Copyright 2003-2006 Sven Anders <anders@anduras.de>
15 * 2003 - Created version 1.0 for Linux 2.4.x.
16 * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE
21 * A Watchdog Timer (WDT) is a hardware circuit that can
25 * Usually a userspace daemon will notify the kernel WDT driver
38 * For an example userspace keep-alive daemon, see:
39 * Documentation/watchdog/wdt.rst
60 /* enable support for minutes as units? */
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Dat91sam9_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
10 * The Watchdog Timer Mode Register can be only written to once. If the
40 #define wdt_read(wdt, field) \ argument
41 readl_relaxed((wdt)->base + (field))
43 writel_relaxed((val), (wdt)->base + (field))
52 #define secs_to_ticks(s) ((s) ? (((s) << 8) - 1) : 0)
77 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
88 unsigned long heartbeat; /* WDT heartbeat in jiffies */
98 struct at91wdt *wdt = (struct at91wdt *)dev_id; in wdt_interrupt() local
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Drzv2h_wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/V2H(P) WDT Watchdog Driver
19 #define WDTRR 0x00 /* WDT Refresh Register RW, 8 */
20 #define WDTCR 0x02 /* WDT Control Register RW, 16 */
21 #define WDTSR 0x04 /* WDT Status Register RW, 16 */
22 #define WDTRCR 0x06 /* WDT Reset Control Register RW, 8 */
45 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
61 * The down-counter is refreshed and starts counting operation on in rzv2h_wdt_ping()
64 writeb(0x0, priv->base + WDTRR); in rzv2h_wdt_ping()
65 writeb(0xFF, priv->base + WDTRR); in rzv2h_wdt_ping()
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Dmeson_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
38 unsigned int enable; member
44 .enable = BIT(22),
50 .enable = BIT(19),
67 tc_reboot |= meson_wdt->data->enable; in meson_wdt_restart()
70 writel(tc_reboot, meson_wdt->wdt_base + MESON_WDT_TC); in meson_wdt_restart()
81 writel(0, meson_wdt->wdt_base + MESON_WDT_RESET); in meson_wdt_ping()
92 reg = readl(meson_wdt->wdt_base + MESON_WDT_TC); in meson_wdt_change_timeout()
93 reg &= ~meson_wdt->data->terminal_count_mask; in meson_wdt_change_timeout()
94 reg |= MESON_SEC_TO_TC(timeout, meson_wdt->data->count_unit); in meson_wdt_change_timeout()
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Dpc87413_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NS pc87413-wdt Watchdog Timer driver for Linux 2.6.x.x
5 * This code is based on wdt.c with original copyright.
12 * This material is provided "AS-IS" and at no charge.
41 #define MODNAME "pc87413 WDT"
42 #define DPFX MODNAME " - DEBUG: "
48 #define WDCTL 0x10 /* Watchdog-Timer-Control-Register */
55 static int swc_base_addr = -1;
66 /* -- Low level function ----------------------------------------*/
74 /* Step 1: Select multiple pin,pin55,as WDT output */ in pc87413_select_wdt_out()
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Dkeembay_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Intel Keem Bay non-secure watchdog.
8 #include <linux/arm-smccc.h>
20 /* Non-secure watchdog register offsets */
47 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default = "
59 static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset) in keembay_wdt_readl() argument
61 return readl(wdt->base + offset); in keembay_wdt_readl()
64 static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val) in keembay_wdt_writel() argument
66 writel(WDT_UNLOCK, wdt->base + TIM_SAFE); in keembay_wdt_writel()
67 writel(val, wdt->base + offset); in keembay_wdt_writel()
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Dbd9576_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/mfd/rohm-bd957x.h>
20 "Watchdog cannot be stopped once started (default=\"false\")");
37 gpiod_set_value_cansleep(priv->gpiod_en, 0); in bd9576_wdt_disable()
45 gpiod_set_value_cansleep(priv->gpiod_ping, 1); in bd9576_wdt_ping()
46 gpiod_set_value_cansleep(priv->gpiod_ping, 0); in bd9576_wdt_ping()
55 gpiod_set_value_cansleep(priv->gpiod_en, 1); in bd9576_wdt_start()
97 return -EINVAL; in find_closest_fast()
113 return -EINVAL; in find_closest_slow_by_fast()
141 return -EINVAL; in find_closest_slow()
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Di6300esb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * based on i810-tco.c which is in turn based on softdog.c
12 * 6300ESB chip : document number 300641-004
46 #define ESB_LOCK_REG 0x68 /* WDT lock register */
49 #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
50 #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
51 #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
52 #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
56 #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
60 #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
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Dmtk_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dt-bindings/reset/mt2712-resets.h>
13 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
14 #include <dt-bindings/reset/mt7986-resets.h>
15 #include <dt-bindings/reset/mt8183-resets.h>
16 #include <dt-bindings/reset/mt8186-resets.h>
17 #include <dt-bindings/reset/mt8188-resets.h>
18 #include <dt-bindings/reset/mt8192-resets.h>
19 #include <dt-bindings/reset/mt8195-resets.h>
29 #include <linux/reset-controller.h>
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Dorion_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
30 #define INTERNAL_REGS_MASK ~(SZ_1M - 1)
70 struct watchdog_device wdt; member
84 dev->clk = clk_get(&pdev->dev, NULL); in orion_wdt_clock_init()
85 if (IS_ERR(dev->clk)) in orion_wdt_clock_init()
86 return PTR_ERR(dev->clk); in orion_wdt_clock_init()
87 ret = clk_prepare_enable(dev->clk); in orion_wdt_clock_init()
89 clk_put(dev->clk); in orion_wdt_clock_init()
93 dev->clk_rate = clk_get_rate(dev->clk); in orion_wdt_clock_init()
102 dev->clk = clk_get(&pdev->dev, NULL); in armada370_wdt_clock_init()
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Ds3c2410_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 #include <linux/soc/samsung/exynos-pmu.h>
80 * DOC: Quirk flags for different Samsung watchdog IP-cores
85 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk
91 * clear the interrupt once the interrupt service routine is complete. It's
92 * write-only, writing any values to this register clears the interrupt, but
96 * WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST,
106 * register. If 'mask_bit' bit is set, PMU will disable WDT reset when
110 * with "watchdog counter enable" bit. That bit should be set to make watchdog
144 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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Dwafer5823wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * ICP Wafer 5823 Single Board Computer WDT driver
7 * (c) Copyright 2002 Justin Cormack <justin@street-vision.com>
11 * Based on advantechwdt.c which is based on wdt.c.
14 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
19 * "AS-IS" and at no charge.
40 #define WATCHDOG_NAME "Wafer 5823 WDT"
49 * You must set these - there is no sane way to probe for this board.
51 * To enable, write the timeout value in seconds (1 to 255) to I/O
69 "Watchdog cannot be stopped once started (default="
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Darmada_37xx_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
35 * Counters ID 2 and 3 are enabled by default even before U-Boot loads,
72 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
76 struct watchdog_device wdt; member
89 * when low is read, high is latched into flip-flops so that it can be in get_counter_value()
92 val = readl(dev->reg + CNTR_COUNT_LOW(id)); in get_counter_value()
93 val |= ((u64)readl(dev->reg + CNTR_COUNT_HIGH(id))) << 32; in get_counter_value()
100 writel(val & 0xffffffff, dev->reg + CNTR_COUNT_LOW(id)); in set_counter_value()
101 writel(val >> 32, dev->reg + CNTR_COUNT_HIGH(id)); in set_counter_value()
108 reg = readl(dev->reg + CNTR_CTRL(id)); in counter_enable()
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Dmt7621_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Ralink MT7621/MT7628 built-in hardware watchdog timer
38 struct watchdog_device wdt; member
44 "Watchdog cannot be stopped once started (default="
61 rt_wdt_w32(drvdata->base, TIMER_REG_TMRSTAT, TMR1CTL_RESTART); in mt7621_wdt_ping()
70 w->timeout = t; in mt7621_wdt_set_timeout()
71 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1LOAD, t * 1000); in mt7621_wdt_set_timeout()
83 rt_wdt_w32(drvdata->base, TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT); in mt7621_wdt_start()
85 mt7621_wdt_set_timeout(w, w->timeout); in mt7621_wdt_start()
87 t = rt_wdt_r32(drvdata->base, TIMER_REG_TMR1CTL); in mt7621_wdt_start()
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Dacquirewdt.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on wdt.c. Original copyright messages:
12 * "AS-IS" and at no charge.
16 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
18 * Can't add timeout - driver doesn't allow changing value
23 * The Watch-Dog Timer is provided to ensure that standalone
28 * reset (cold boot) or a non-maskable interrupt (NMI) to bring the
31 * The Watch-Dog Timer is controlled by two I/O Ports.
32 * 443 hex - Read - Enable or refresh the Watch-Dog Timer
33 * 043 hex - Read - Disable the Watch-Dog Timer
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