Home
last modified time | relevance | path

Searched full:wave (Results 1 – 25 of 137) sorted by relevance

123456

/linux-6.12.1/sound/pci/
Dad1889.h9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
12 #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
13 #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
15 #define AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */
25 #define AD_DS_WADA 0x04 /* wave channel mix attenuation */
26 #define AD_DS_WADA_RWAM 0x0080 /* right wave mute */
27 #define AD_DS_WADA_RWAA 0x001f /* right wave attenuation */
28 #define AD_DS_WADA_LWAM 0x8000 /* left wave mute */
29 #define AD_DS_WADA_LWAA 0x3e00 /* left wave attenuation */
[all …]
Dad1889.c90 struct ad1889_register_state wave; member
187 /* Disable wave channel */ in ad1889_channel_reset()
190 chip->wave.reg = reg; in ad1889_channel_reset()
358 chip->wave.size = size; in snd_ad1889_playback_prepare()
359 chip->wave.reg = reg; in snd_ad1889_playback_prepare()
360 chip->wave.addr = rt->dma_addr; in snd_ad1889_playback_prepare()
362 ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); in snd_ad1889_playback_prepare()
368 ad1889_load_wave_buffer_address(chip, chip->wave.addr); in snd_ad1889_playback_prepare()
379 chip->wave.addr, count, size, reg, rt->rate); in snd_ad1889_playback_prepare()
433 The WSMC "WAEN" bit triggers DMA Wave On/Off */
[all …]
Dsis7019.h160 /* Wave Engine Config and Control Register */
182 /* Wave Engine Volume Control Register */
189 /* Wave Engine Interrupt Status Registers */
305 /* Wave Engine Control Parameters (parameter RAM) */
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_3_cleaner_shader.asm33 // Each wave clears SGPRs 0 - 95. Because there are 4 waves/SIMD, this is physical SGPRs 0-3…
34 // Each wave clears 128 VGPRs, so all 512 in the SIMD
35 // The first wave of the workgroup clears its 64KB of LDS
37 // before any wave in the workgroup could end. Without this, it is possible not all SGPRs…
56 …s_cbranch_scc0 label_0023 // Clean VGPRs and LDS if sgpr0 of wave is set, …
84 …s_cbranch_scc0 label_clean_sgpr_1 // Clean LDS if its first wave of ThreadGroup/Wo…
Dgfx_v9_4_2.c422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
431 dev_dbg(adev->dev, "wave assignment:\n"); in gfx_v9_4_2_log_wave_assignment()
439 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
468 for (wave = 0; wave < WAVE_ID_MAX; wave++) { in gfx_v9_4_2_wait_for_waves_assigned()
469 if (((1 << wave) & mask) && in gfx_v9_4_2_wait_for_waves_assigned()
482 dev_err(adev->dev, "actual wave num: %d, expected wave num: %d\n", in gfx_v9_4_2_wait_for_waves_assigned()
535 dev_err(adev->dev, "wave coverage failed when clear first 224 sgprs\n"); in gfx_v9_4_2_do_sgprs_init()
559 dev_err(adev->dev, "wave coverage failed when clear first 576 sgprs\n"); in gfx_v9_4_2_do_sgprs_init()
600 dev_err(adev->dev, "wave coverage failed when clear first 256 sgprs\n"); in gfx_v9_4_2_do_sgprs_init()
[all …]
Damdgpu_amdkfd_gfx_v9.c652 * GFX9 helper for wave launch stall requirements on debug trap setting.
658 * 0-unstall wave launch (enable), 1-stall wave launch (disable).
785 /* We need to preserve wave launch mode stall settings. */ in kgd_gfx_v9_set_wave_launch_trap_override()
898 * gws_wait_time -- Wait Count for Global Wave Syncs.
900 * sch_wave_wait_time -- Wait Count for Scheduling Wave Message.
902 * deq_retry_wait_time -- Wait Count for Global Wave Syncs.
948 * @vmid: Output parameter updated with VMID of queue whose wave count
994 * to an inaccurate wave count. Following is a high-level sequence:
997 * In the sequence above wave count obtained from time T1 will be incorrectly
998 * lost or added to total wave count.
[all …]
Damdgpu_debugfs.c434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
1034 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
1041 * The offset being sought changes which wave that the status data
1048 * Bits 31..36: WAVE ID selector
1052 * Followed by WAVE STATUS registers relevant to the GFX IP version
1061 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
1071 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; in amdgpu_debugfs_wave_read()
1092 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
[all …]
Dgfx_v6_0.c2945 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2948 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
2956 uint32_t wave, uint32_t thread, in wave_read_regs() argument
2960 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
2970 …data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int… in gfx_v6_0_read_wave_data() argument
2972 /* type 0 wave data */ in gfx_v6_0_read_wave_data()
2974 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
[all …]
Damdgpu_amdkfd_gfx_v10.c715 * GFX10 helper for wave launch stall requirements on debug trap setting.
721 * 0-unstall wave launch (enable), 1-stall wave launch (disable).
851 /* We need to preserve wave launch mode stall settings. */ in kgd_gfx_v10_set_wave_launch_trap_override()
1010 * gws_wait_time -- Wait Count for Global Wave Syncs.
1012 * sch_wave_wait_time -- Wait Count for Scheduling Wave Message.
1014 * deq_retry_wait_time -- Wait Count for Global Wave Syncs.
/linux-6.12.1/include/uapi/sound/
Dsfnt_info.h74 /* wave table envelope & effect parameters to control EMU8000 */
100 /* wave table parameters: 92 bytes */
142 * sample wave information
145 /* wave table sample header: 32 bytes */
154 #define SNDRV_SFNT_SAMPLE_8BITS 1 /* wave data is 8bits */
155 #define SNDRV_SFNT_SAMPLE_UNSIGNED 2 /* wave data is unsigned */
/linux-6.12.1/arch/m68k/mac/
Dmacboing.c23 * dumb triangular wave table
137 * init the wave table with a simple triangular wave in mac_init_asc()
138 * A sine wave would sure be nicer here ... in mac_init_asc()
263 * already load the wave table, or at least call this one...
264 * This piece keeps reloading the wave table until done.
/linux-6.12.1/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
19 wave input on the OSCIN pin instead of using a crystal oscillator.
61 ti,clkmode-square-wave;
/linux-6.12.1/sound/pci/emu10k1/
Demu10k1.c75 struct snd_seq_device *wave = NULL; in snd_card_emu10k1_probe() local
150 sizeof(struct snd_emu10k1_synth_arg), &wave) < 0 || in snd_card_emu10k1_probe()
151 wave == NULL) { in snd_card_emu10k1_probe()
156 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in snd_card_emu10k1_probe()
157 strcpy(wave->name, "Emu-10k1 Synth"); in snd_card_emu10k1_probe()
/linux-6.12.1/drivers/gpu/drm/amd/amdkfd/
Dkfd_int_process_v10.c34 * Wave - Generated by S_SENDMSG through a shader program
41 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
44 * PRIV bit indicates that Wave S_SEND or error occurred within trap
50 * Wave - user data sent from m0 via S_SENDMSG
53 * The other context_id bits show coordinates (SE/SH/CU/SIMD/WGP) for wave
109 /* GFX10 SQ interrupt ENC type bit (context_id1[7:6]) for wave s_sendmsg */
Dcwsr_trap_handler_gfx9.asm212 // Host trap may occur while wave is halted.
220 // Wave is halted but neither host trap nor SAVECTX is raised.
232 // and debugger (host trap, wave start/end, trap after instruction)
233 // exceptions always cause the wave to enter the trap handler.
244 // Maskable exceptions only cause the wave to enter the trap handler if
266 // Second-level trap will halt wave and RFE, re-entering for SAVECTX.
307 // If not caused by trap then halt wave to prevent re-entry.
366 …ot enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit…
435 /* the first wave in the threadgroup */
436 …d_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit
[all …]
Dkfd_int_process_v11.c37 * Wave - Generated by S_SENDMSG through a shader program
44 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
47 * PRIV bit indicates that Wave S_SEND or error occurred within trap
53 * Wave - user data sent from m0 via S_SENDMSG (context_id0[23:0])
56 * The other context_id bits show coordinates (SE/SH/CU/SIMD/WGP) for wave
Dkfd_int_process_v9.c38 * Wave - Generated by S_SENDMSG through a shader program
45 * Encoding type (0 = Auto, 1 = Wave, 2 = Error)
48 * PRIV bit indicates that Wave S_SEND or error occurred within trap
54 * Wave - user data sent from m0 via S_SENDMSG
57 * The other context_id bits show coordinates (SE/SH/CU/SIMD/WAVE) for wave
Dcwsr_trap_handler_gfx8.asm226 …ot enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit…
288 /* the first wave in the threadgroup */
290 … s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit
291 …, s_save_tmp, tba_hi // save first wave bit to tba_hi.bits[…
293 …xec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_…
341 // each wave will alloc 4 vgprs at least...
377 // first wave do LDS save;
487 /* the first wave in the threadgroup */
666 …rier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FI…
Dcwsr_trap_handler_gfx10.asm307 // Host trap may occur while wave is halted.
319 // Wave is halted but neither host trap nor SAVECTX is raised.
331 // and xnack_error exceptions always cause the wave to enter the trap
337 // Maskable exceptions only cause the wave to enter the trap handler if
371 // Second-level trap will halt wave and RFE, re-entering for SAVECTX.
423 // If not caused by trap then halt wave to prevent re-entry.
511 // SQ hang, since the 7,8th wave could not get arbit to exec inst, while
823 // first wave do LDS save;
1324 … //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG
1370 // Only the first wave needs to restore the workgroup barrier.
/linux-6.12.1/Documentation/devicetree/bindings/media/
Dcnm,wave521c.yaml7 title: Chips&Media Wave 5 Series multi-standard codec IP
14 The Chips&Media WAVE codec IP is a multi format video encoder/decoder
/linux-6.12.1/sound/pci/au88x0/
Dau88x0.c267 sizeof(snd_vortex_synth_arg_t), &wave) < 0 in __snd_vortex_probe()
268 || wave == NULL) { in __snd_vortex_probe()
273 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); in __snd_vortex_probe()
274 strcpy(wave->name, "Aureal Synth"); in __snd_vortex_probe()
/linux-6.12.1/include/uapi/linux/
Dxilinx-v4l2-controls.h57 /* Set starting point of sine wave for horizontal component */
61 /* Set starting point of sine wave for vertical component */
/linux-6.12.1/Documentation/sound/designs/
Doss-emulation.rst287 proc file. For example, to map "Wave Playback" to the PCM volume,
291 % echo 'VOLUME "Wave Playback" 0' > /proc/asound/card0/oss_mixer
295 example, both "Wave Playback Volume" and "Wave Playback Switch" will
/linux-6.12.1/Documentation/sound/cards/
Dsb-live-mixer.rst62 ``name='Wave Playback Volume',index=0``
68 ``name='Wave Surround Playback Volume',index=0``
75 ``name='Wave Center Playback Volume',index=0``
82 ``name='Wave LFE Playback Volume',index=0``
89 ``name='Wave Capture Volume',index=0``, ``name='Wave Capture Switch',index=0``
/linux-6.12.1/drivers/clk/sunxi-ng/
Dccu_sdm.c82 * The datasheets do not explain what the "wave top" and "wave bottom"

123456