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/linux-6.12.1/arch/arm/boot/dts/nxp/vf/
Dvfxxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "vf610-pinfunc.h"
6 #include <dt-bindings/clock/vf610-clock.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
[all …]
Dvf610-zii-ssmb-dtu.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 * SSMB - SPU3 Switch Management Board
7 * DTU - Digital Tapping Unit
9 * Copyright (C) 2015-2019 Zodiac Inflight Innovations
11 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
15 /dts-v1/;
16 #include "vf610.dtsi"
19 model = "ZII VF610 SSMB DTU Board";
20 compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610";
23 stdout-path = &uart0;
[all …]
Dvf610-zii-ssmb-spu3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 * SSMB - SPU3 Switch Management Board
7 * SPU - Seat Power Unit
11 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
15 /dts-v1/;
16 #include "vf610.dtsi"
19 model = "ZII VF610 SSMB SPU3 Board";
20 compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";
23 stdout-path = &uart0;
31 gpio-leds {
[all …]
Dvf610-zii-spb4.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 * SPB - Seat Power Box
11 /dts-v1/;
12 #include "vf610.dtsi"
15 model = "ZII VF610 SPB4 Board";
16 compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";
19 stdout-path = &uart0;
27 gpio-leds {
28 compatible = "gpio-leds";
29 pinctrl-0 = <&pinctrl_leds_debug>;
[all …]
Dvf610-zii-cfu1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include "vf610.dtsi"
11 model = "ZII VF610 CFU1 Board";
12 compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610";
15 stdout-path = &uart0;
23 gpio-leds {
24 compatible = "gpio-leds";
25 pinctrl-0 = <&pinctrl_leds_debug>;
26 pinctrl-names = "default";
[all …]
Dvf610-zii-dev-rev-c.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "vf610-zii-dev.dtsi"
10 model = "ZII VF610 Development Board, Rev C";
11 compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
13 mdio-mux {
14 compatible = "mdio-mux-gpio";
15 pinctrl-0 = <&pinctrl_mdio_mux>;
16 pinctrl-names = "default";
20 mdio-parent-bus = <&mdio1>;
[all …]
Dvf610-zii-dev-rev-b.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "vf610-zii-dev.dtsi"
10 model = "ZII VF610 Development Board, Rev B";
11 compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
13 mdio-mux {
14 compatible = "mdio-mux-gpio";
15 pinctrl-0 = <&pinctrl_mdio_mux>;
16 pinctrl-names = "default";
21 mdio-parent-bus = <&mdio1>;
[all …]
Dvf610-bk4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "vf610.dtsi"
12 compatible = "lwn,bk4", "fsl,vf610";
15 stdout-path = &uart1;
23 audio_ext: oscillator-audio {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <24576000>;
29 enet_ext: oscillator-ethernet {
[all …]
Dvf610-zii-dev.dtsi4 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
7 * This file is dual-licensed: you can use it either under the terms
45 #include "vf610.dtsi"
49 stdout-path = "serial0:115200n8";
57 gpio-leds {
58 compatible = "gpio-leds";
59 pinctrl-0 = <&pinctrl_leds_debug>;
60 pinctrl-names = "default";
62 led-debug {
65 linux,default-trigger = "heartbeat";
[all …]
Dvf610-zii-scu4-aib.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations
5 /dts-v1/;
6 #include "vf610.dtsi"
9 model = "ZII VF610 SCU4 AIB";
10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
13 stdout-path = &uart0;
21 gpio-leds {
22 compatible = "gpio-leds";
23 pinctrl-0 = <&pinctrl_leds_debug>;
[all …]
Dvf-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2014-2020 Toradex
14 compatible = "pwm-backlight";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_gpio_bl_on>;
18 enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
22 reg_module_3v3: regulator-module-3v3 {
23 compatible = "regulator-fixed";
24 regulator-name = "+V3.3";
25 regulator-min-microvolt = <3300000>;
[all …]
Dvf-colibri-eval-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2014-2020 Toradex
8 stdout-path = "serial0:115200n8";
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <16000000>;
23 remote-endpoint = <&dcu_out>;
28 reg_3v3: regulator-3v3 {
29 compatible = "regulator-fixed";
30 regulator-name = "3.3V";
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dgpio-vf610.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale VF610 PORT/GPIO module
10 - Stefan Agner <stefan@agner.ch>
13 The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
14 functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
17 Note: Each GPIO port should have an alias correctly numbered in "aliases"
23 - const: fsl,imx8ulp-gpio
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/ls/
Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]
Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
[all …]
Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-vf610.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale vf610 GPIO support through PORT and GPIO
12 #include <linux/gpio/driver.h>
81 { .compatible = "fsl,vf610-gpio", .data = &vf610_data },
82 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
83 { .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, },
97 static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) in vf610_gpio_get() argument
100 u32 mask = BIT(gpio); in vf610_gpio_get()
103 if (port->sdata->have_paddr) { in vf610_gpio_get()
104 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); in vf610_gpio_get()
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/can/
Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx95-flexcan
21 - fsl,imx93-flexcan
22 - fsl,imx8qm-flexcan
[all …]
/linux-6.12.1/drivers/mtd/nand/raw/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
126 include NAND flash controllers with built-in hardware ECC
161 - PXA3xx processors (NFCv1)
162 - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2)
163 - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2)
229 Controller Module with built-in hardware ECC capabilities.
240 with built-in hardware ECC capabilities.
250 processor localbus with User-Programmable Machine support.
253 tristate "Freescale VF610/MPC5125 NAND controller"
[all …]

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