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/linux-6.12.1/arch/arm/boot/dts/socionext/
Duniphier-ld4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-ld4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
[all …]
Duniphier-sld8.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier sLD8 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-sld8";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
[all …]
Duniphier-pro4.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro4 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "socionext,uniphier-pro4";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
[all …]
Duniphier-pxs2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs2 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs2";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
[all …]
Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
[all …]
Duniphier-ld4-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD4 Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-ld4.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier LD4 Reference Board";
15 compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";
18 stdout-path = "serial0:115200n8";
[all …]
Duniphier-sld8-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier sLD8 Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-sld8.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier sLD8 Reference Board";
15 compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8";
18 stdout-path = "serial0:115200n8";
[all …]
Duniphier-ld6b-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD6b Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-ld6b.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier LD6b Reference Board";
15 compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";
18 stdout-path = "serial0:115200n8";
[all …]
Duniphier-pro4-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro4 Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-pro4.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier Pro4 Reference Board";
15 compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";
18 stdout-path = "serial0:115200n8";
[all …]
Duniphier-support-card.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Support Card (Expansion Board)
5 // Copyright (C) 2015-2017 Socionext Inc.
15 phy-mode = "mii";
16 reg-io-width = <4>;
17 interrupt-parent = <&gpio>;
23 clock-frequency = <12288000>;
24 reg-shift = <1>;
25 interrupt-parent = <&gpio>;
/linux-6.12.1/arch/arm64/boot/dts/socionext/
Duniphier-ld11.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "socionext,uniphier-ld11";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
[all …]
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 SoC
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
[all …]
Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
Duniphier-ld20-global.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 Global Board
5 // Copyright (C) 2015-2017 Socionext Inc.
9 /dts-v1/;
10 #include <dt-bindings/gpio/uniphier-gpio.h>
11 #include "uniphier-ld20.dtsi"
14 model = "UniPhier LD20 Global Board (REF_LD20_GP)";
15 compatible = "socionext,uniphier-ld20-global",
16 "socionext,uniphier-ld20";
19 stdout-path = "serial0:115200n8";
[all …]
Duniphier-ld11-global.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 Global Board
5 // Copyright (C) 2016-2017 Socionext Inc.
9 /dts-v1/;
10 #include <dt-bindings/gpio/uniphier-gpio.h>
11 #include "uniphier-ld11.dtsi"
14 model = "UniPhier LD11 Global Board (REF_LD11_GP)";
15 compatible = "socionext,uniphier-ld11-global",
16 "socionext,uniphier-ld11";
19 stdout-path = "serial0:115200n8";
[all …]
Duniphier-ld20-akebi96.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Derived from uniphier-ld20-global.dts.
7 // Copyright (C) 2015-2017 Socionext Inc.
8 // Copyright (C) 2019-2020 Linaro Ltd.
10 /dts-v1/;
11 #include <dt-bindings/gpio/uniphier-gpio.h>
12 #include "uniphier-ld20.dtsi"
16 compatible = "socionext,uniphier-ld20-akebi96",
17 "socionext,uniphier-ld20";
20 stdout-path = "serial0:115200n8";
[all …]
Duniphier-ld11-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD11 Reference Board
8 /dts-v1/;
9 #include "uniphier-ld11.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier LD11 Reference Board";
15 compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11";
18 stdout-path = "serial0:115200n8";
53 &gpio {
[all …]
Duniphier-ld20-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier LD20 Reference Board
5 // Copyright (C) 2015-2016 Socionext Inc.
8 /dts-v1/;
9 #include "uniphier-ld20.dtsi"
10 #include "uniphier-ref-daughter.dtsi"
11 #include "uniphier-support-card.dtsi"
14 model = "UniPhier LD20 Reference Board";
15 compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
18 stdout-path = "serial0:115200n8";
[all …]
Duniphier-pxs3-ref.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier PXs3 Reference Board
8 /dts-v1/;
9 #include "uniphier-pxs3.dtsi"
10 #include "uniphier-support-card.dtsi"
13 model = "UniPhier PXs3 Reference Board";
14 compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
17 stdout-path = "serial0:115200n8";
70 &gpio {
71 xirq4-hog {
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dsocionext,uniphier-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier GPIO controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
14 pattern: "^gpio@[0-9a-f]+$"
17 const: socionext,uniphier-gpio
22 gpio-controller: true
24 "#gpio-cells":
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-uniphier.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/gpio/driver.h>
16 #include <dt-bindings/gpio/uniphier-gpio.h>
43 * Unfortunately, the GPIO port registers are not contiguous because in uniphier_gpio_bank_to_reg()
44 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. in uniphier_gpio_bank_to_reg()
65 spin_lock_irqsave(&priv->lock, flags); in uniphier_gpio_reg_update()
66 tmp = readl(priv->regs + reg); in uniphier_gpio_reg_update()
69 writel(tmp, priv->regs + reg); in uniphier_gpio_reg_update()
70 spin_unlock_irqrestore(&priv->lock, flags); in uniphier_gpio_reg_update()
107 return !!(readl(priv->regs + reg_offset) & mask); in uniphier_gpio_offset_read()
[all …]
/linux-6.12.1/drivers/reset/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
83 tristate "GPIO reset controller"
87 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
90 If compiled as module, it will be called reset-gpio.
132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
221 Raspberry Pi 4's co-processor controls some of the board's HW
224 interfacing with RPi4's co-processor and model these firmware
255 - Altera SoCFPGAs
256 - ASPEED BMC SoCs
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += hisilicon/
4 obj-y += starfive/
5 obj-y += sti/
6 obj-y += tegra/
7 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
8 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
9 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
[all …]
/linux-6.12.1/drivers/bus/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
114 cores. This bus is for per-CPU tightly coupled devices such as the
[all …]
/linux-6.12.1/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
155 supports spi-mem interface.
231 With a few GPIO pins, your system can bitbang the SPI protocol.
232 Select this to get SPI support through I/O pins (GPIO, parallel
[all …]

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