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/linux-6.12.1/tools/testing/selftests/timers/
Dadjtick.c7 * $ gcc adjtick.c -o adjtick -lrt
11 * the Free Software Foundation, either version 2 of the License, or
40 val = -val; in llabs()
66 return end_ns - start_ns; in diff_timespec()
90 tmp = (ts_to_nsec(start) + ts_to_nsec(end))/2; in get_monotonic_and_raw()
110 eppm = (delta1*MILLION)/delta2 - MILLION; in get_ppm_drift()
118 struct timex tx1; in check_tick_adj() local
120 tx1.modes = ADJ_TICK; in check_tick_adj()
121 tx1.modes |= ADJ_OFFSET; in check_tick_adj()
122 tx1.modes |= ADJ_FREQUENCY; in check_tick_adj()
[all …]
Draw_skew.c9 * $ gcc raw_skew.c -o raw_skew -lrt
13 * the Free Software Foundation, either version 2 of the License, or
36 __x < 0 ? -(-__x >> __s) : __x >> __s; \
42 val = -val; in llabs()
66 return end_ns - start_ns; in diff_timespec()
86 tmp = (ts_to_nsec(start) + ts_to_nsec(end))/2; in get_monotonic_and_raw()
96 struct timex tx1, tx2; in main() local
102 return -1; in main()
105 tx1.modes = 0; in main()
106 adjtimex(&tx1); in main()
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/linux-6.12.1/sound/soc/tegra/
Dtegra210_ahub.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_ahub.c - Tegra210 AHUB driver
5 // Copyright (c) 2020-2024, NVIDIA CORPORATION. All rights reserved.
22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; in tegra_ahub_get_value_enum()
29 for (i = 0; i < ahub->soc_data->reg_count; i++) { in tegra_ahub_get_value_enum()
32 reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); in tegra_ahub_get_value_enum()
34 reg_val &= ahub->soc_data->mask[i]; in tegra_ahub_get_value_enum()
38 (8 * cmpnt->val_bytes * i); in tegra_ahub_get_value_enum()
44 for (i = 0; i < e->items; i++) { in tegra_ahub_get_value_enum()
45 if (bit_pos == e->values[i]) { in tegra_ahub_get_value_enum()
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Md Danish Anwar <danishanwar@ti.com>
13 Ethernet based on the Programmable Real-Time Unit and Industrial
19 - ti,am642-icssg-prueth # for AM64x SoC family
20 - ti,am654-icssg-prueth # for AM65x SoC family
21 - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
32 dma-names:
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/linux-6.12.1/Documentation/devicetree/bindings/net/can/
Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
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/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am65-iot2050-common-pg1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2021-2023
11 #include "k3-am65-iot2050-dp.dtsi"
18 no-1-8-v;
46 compatible = "ti,am654-sr1-icssg-prueth";
49 firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf",
50 "ti-pruss/am65x-rtu0-prueth-fw.elf",
51 "ti-pruss/am65x-pru1-prueth-fw.elf",
52 "ti-pruss/am65x-rtu1-prueth-fw.elf";
54 ti,pruss-gp-mux-sel = <2>, /* MII mode */
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Dk3-am654-idk.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
18 ethernet4 = "/icssg0-eth/ethernet-ports/port@1";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
20 ethernet6 = "/icssg1-eth/ethernet-ports/port@1";
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Dk3-am654-icssg2.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-pinctrl.h"
16 ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
17 ethernet2 = "/icssg2-eth/ethernet-ports/port@1";
20 /* Ethernet node on PRU-ICSSG2 */
21 icssg2_eth: icssg2-eth {
22 compatible = "ti,am654-icssg-prueth";
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Dk3-am642-phyboard-electra-rdk.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 PHYTEC America, LLC - https://www.phytec.com
6 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH
10 * https://www.phytec.com/product/phyboard-am64x
13 /dts-v1/;
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/leds/common.h>
18 #include <dt-bindings/leds/leds-pca9532.h>
19 #include <dt-bindings/phy/phy.h>
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/linux-6.12.1/drivers/phy/qualcomm/
Dphy-qcom-edp.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
17 #include <linux/phy/phy-dp.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp-dp-phy.h"
26 #include "phy-qcom-qmp-qserdes-com-v4.h"
27 #include "phy-qcom-qmp-qserdes-com-v6.h"
105 void __iomem *tx1; member
113 struct clk_bulk_data clks[2];
114 struct regulator_bulk_data supplies[2];
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/linux-6.12.1/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8-ss-vpu.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 vpu: vpu@2c000000 {
8 #address-cells = <1>;
9 #size-cells = <1>;
12 power-domains = <&pd IMX_SC_R_VPU>;
15 mu_m0: mailbox@2d000000 {
16 compatible = "fsl,imx6sx-mu";
19 #mbox-cells = <2>;
20 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
24 mu1_m0: mailbox@2d020000 {
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/linux-6.12.1/Documentation/devicetree/bindings/media/
Damphion,vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
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/linux-6.12.1/drivers/net/ethernet/8390/
Dlib8390.c1 // SPDX-License-Identifier: GPL-1.0+
5 Written 1992-94 by Donald Becker.
16 This is the chip-specific code for many 8390-based ethernet adaptors.
17 This is not a complete driver, it must be combined with board-specific
23 you have found something that needs changing. -- PG
39 Paul Gortmaker : add kmod support for auto-loading of the 8390
79 /* These are the operational function interfaces to board-specific
88 "page" value uses the 8390's 256-byte pages.
97 #define ei_reset_8390 (ei_local->reset_8390)
98 #define ei_block_output (ei_local->block_output)
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Daxnet_cs.c1 // SPDX-License-Identifier: GPL-1.0+
5 A PCMCIA ethernet driver for Asix AX88190-based cards
7 The Asix AX88190 is a NS8390-derived chipset with a few nasty
14 Copyright (C) 2001 David A. Hinds -- dahinds@users.sourceforge.net
52 #define AXNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */
146 dev_dbg(&link->dev, "axnet_attach()\n"); in axnet_probe()
150 return -ENOMEM; in axnet_probe()
153 spin_lock_init(&ei_local->page_lock); in axnet_probe()
156 info->p_dev = link; in axnet_probe()
157 link->priv = dev; in axnet_probe()
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/linux-6.12.1/Documentation/driver-api/dmaengine/
Dpxa_dma.rst2 PXA/MMP - DMA Slave controller
21 This implies that even if an irq/tasklet is triggered by end of tx1, but
22 at the time of irq/dma tx2 is already finished, tx1->complete() and
23 tx2->complete() should be called.
36 A driver should be able to request a priority, especially the real-time
46 b) Transfer anatomy for a scatter-gather transfer
50 +------------+-----+---------------+----------------+-----------------+
51 | desc-sg[0] | ... | desc-sg[last] | status updater | finisher/linker |
52 +------------+-----+---------------+----------------+-----------------+
54 This structure is pointed by dma->sg_cpu.
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/linux-6.12.1/Documentation/devicetree/bindings/usb/
Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
20 vcc-supply:
23 enable-gpios: true
24 orientation-switch: true
25 retimer-switch: true
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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^admaif@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-admaif
28 - nvidia,tegra186-admaif
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Dnvidia,tegra-audio-graph-card.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Sameer Pujar <spujar@nvidia.com>
19 - $ref: audio-graph.yaml#
24 - nvidia,tegra210-audio-graph-card
25 - nvidia,tegra186-audio-graph-card
28 minItems: 2
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/linux-6.12.1/include/sound/
Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 #define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */
26 #define AK4114_REG_TXCSB2 0x0f /* TX channel status byte 2 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
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/linux-6.12.1/sound/firewire/dice/
Ddice-alesis.c1 // SPDX-License-Identifier: GPL-2.0
3 * dice-alesis.c - a part of driver for DICE based devices
13 {8, 4, 0}, /* Tx1 = ADAT1. */
19 {16, 4, 0}, /* Tx1 = ADAT1 + ADAT2 (available at low rate). */
36 memcpy(dice->tx_pcm_chs, alesis_io14_tx_pcm_chs, in snd_dice_detect_alesis_formats()
40 memcpy(dice->tx_pcm_chs, alesis_io26_tx_pcm_chs, in snd_dice_detect_alesis_formats()
46 dice->rx_pcm_chs[0][i] = 8; in snd_dice_detect_alesis_formats()
48 dice->tx_midi_ports[0] = 1; in snd_dice_detect_alesis_formats()
49 dice->rx_midi_ports[0] = 1; in snd_dice_detect_alesis_formats()
58 dice->tx_pcm_chs[0][SND_DICE_RATE_MODE_LOW] = 16; in snd_dice_detect_alesis_mastercontrol_formats()
[all …]
/linux-6.12.1/sound/soc/codecs/
Drk817_codec.c1 // SPDX-License-Identifier: GPL-2.0
32 * I don't have another implementation to compare from the Rockchip sources. Hard-coding for now.
45 if (rk817->mic_in_differential) { in rk817_init()
61 /* Set the PLL pre-divide value (values not documented). */ in rk817_set_component_pll()
73 * 0db~-95db, 0.375db/step, for example:
75 * 0xff: -95dB
78 static const DECLARE_TLV_DB_MINMAX(rk817_vol_tlv, -9500, 0);
82 * 27db~-18db, 3db/step, for example:
83 * 0x0: -18dB
87 static const DECLARE_TLV_DB_MINMAX(rk817_gain_tlv, -1800, 2700);
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Dcs35l41.c1 // SPDX-License-Identifier: GPL-2.0
3 // cs35l41.c -- CS35l41 ALSA SoC audio driver
5 // Copyright 2017-2021 Cirrus Logic, Inc.
22 #include <sound/soc-dapm.h>
164 return -EINVAL; in cs35l41_get_fs_mon_config_index()
169 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200));
176 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"
186 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs35l41_dsp_preload_ev()
192 if (cs35l41->dsp.cs_dsp.booted) in cs35l41_dsp_preload_ev()
197 if (cs35l41->dsp.preloaded) in cs35l41_dsp_preload_ev()
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Dtwl4030.c1 // SPDX-License-Identifier: GPL-2.0-only
28 #include <linux/mfd/twl4030-audio.h>
33 #define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
67 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];
79 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte; in tw4030_init_ctl_cache()
89 return -EIO; in twl4030_read()
98 value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL]; in twl4030_read()
116 if (twl4030->earpiece_enabled) in twl4030_can_write_to_chip()
120 if (twl4030->predrivel_enabled) in twl4030_can_write_to_chip()
124 if (twl4030->predriver_enabled) in twl4030_can_write_to_chip()
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/linux-6.12.1/arch/x86/crypto/
Dtwofish-x86_64-asm_64-3way.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Twofish Cipher 3-way parallel algorithm (x86_64)
10 .file "twofish-x86_64-asm-3way.S"
22 3-way twofish
93 #define g1g2_3(ab, cd, Tx0, Tx1, Tx2, Tx3, Ty0, Ty1, Ty2, Ty3, x, y) \ argument
95 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 0, ab ## 0, x ## 0); \
98 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 1, ab ## 1, x ## 1); \
101 do16bit_ror(32, mov, xor, Tx0, Tx1, RT0, x ## 2, ab ## 2, x ## 2); \
102 do16bit_ror(48, mov, xor, Ty1, Ty2, RT0, y ## 2, ab ## 2, y ## 2); \
104 /* G1,2 && G2,2 */ \
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