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Searched +full:tx +full:- +full:clk +full:- +full:adj +full:- +full:enabled (Results 1 – 12 of 12) sorted by relevance

/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
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Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
24 phy-handle = <&phy1>;
25 phy-mode = "rgmii-id";
26 starfive,tx-use-rgmii-clk;
27 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
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Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 starfive,tx-use-rgmii-clk;
16 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
17 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
29 motorcomm,tx-clk-adj-enabled;
30 motorcomm,tx-clk-10-inverted;
31 motorcomm,tx-clk-100-inverted;
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
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/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
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Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
111 /* SMA1 and UFL1 cannot be set to TX at the same time */ in ice_ptp_set_sma_config_e810t()
114 return -EINVAL; in ice_ptp_set_sma_config_e810t()
119 return -EINVAL; in ice_ptp_set_sma_config_e810t()
138 /* U.FL 1 TX will always enable SMA 1 RX */ in ice_ptp_set_sma_config_e810t()
139 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX"); in ice_ptp_set_sma_config_e810t()
142 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX"); in ice_ptp_set_sma_config_e810t()
145 dev_info(ice_hw_to_dev(hw), "SMA1 TX"); in ice_ptp_set_sma_config_e810t()
165 dev_info(ice_hw_to_dev(hw), "SMA2 TX"); in ice_ptp_set_sma_config_e810t()
170 dev_info(ice_hw_to_dev(hw), "SMA2 TX + U.FL2 RX"); in ice_ptp_set_sma_config_e810t()
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/linux-6.12.1/drivers/net/ethernet/cadence/
Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk.h>
34 #define MACB_TBQP 0x001c /* TX Q Base Address */
101 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
113 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
116 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
117 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
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/linux-6.12.1/drivers/net/phy/
Dmotorcomm.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: Frank <Frank.Sae@motor-comm.com>
22 * ------------------------------------------------------------
26 * ------------------------------------------------------------
28 * ------------------------------------------------------------
104 /* FIBER Auto-Negotiation link partner ability */
122 /* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
125 /* TX Gig-E Delay is bits 7:4, default 0x5
126 * TX Fast-E Delay is bits 15:12, default 0xf
127 * Delay = 150ps * N - 250ps
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/linux-6.12.1/drivers/net/ethernet/ti/
Dam65-cpts.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
23 #include "am65-cpts.h"
164 struct clk *refclk;
201 #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
202 #define am65_cpts_read32(c, r) readl(&(c)->reg->r)
219 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; in am65_cpts_set_add_val()
221 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val); in am65_cpts_set_add_val()
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/linux-6.12.1/drivers/gpu/drm/mcde/
Dmcde_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
2 #include <linux/clk.h>
47 struct clk *hs_clk;
48 struct clk *lp_clk;
73 d = host_to_mcde_dsi(mdsi->host); in mcde_dsi_irq()
75 dev_dbg(d->dev, "%s called\n", __func__); in mcde_dsi_irq()
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
81 dev_dbg(d->dev, "direct command write completed\n"); in mcde_dsi_irq()
84 dev_dbg(d->dev, "direct command TE received\n"); in mcde_dsi_irq()
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/linux-6.12.1/drivers/phy/samsung/
Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk.h>
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
194 /* Exynos9 - GS101 */
324 for (; (tune)->region != PTR_INVALID; ++(tune))
378 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
415 phys[(inst)->index]); in to_usbdrd_phy()
452 return -EINVAL; in exynos5_rate_to_clk()
463 if (!inst->reg_pmu) in exynos5_usbdrd_phy_isol()
468 regmap_update_bits(inst->reg_pmu, inst->pmu_offset, in exynos5_usbdrd_phy_isol()
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/linux-6.12.1/drivers/gpu/drm/bridge/
Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
22 #include <linux/clk.h>
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
129 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
131 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
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