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/linux-6.12.1/drivers/staging/media/tegra-video/
Dtegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * This source file contains Tegra210 supported video formats,
8 * VI and CSI SoC specific data, operations and registers accessors.
17 #include "csi.h"
29 /* Tegra210 VI registers */
40 /* Tegra210 VI CSI registers */
64 /* Tegra210 CSI Pixel Parser registers: Starts from 0x838, offset 0x0 */
92 /* Tegra210 CSI PHY registers */
146 /* Tegra210 VI registers accessors */
150 writel_relaxed(val, chan->vi->iomem + addr); in tegra_vi_write()
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Dvi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <media/media-entity.h>
17 #include <media/v4l2-async.h>
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-dev.h>
21 #include <media/v4l2-subdev.h>
22 #include <media/videobuf2-v4l2.h>
24 #include "csi.h"
44 * struct tegra_vi_ops - Tegra VI operations
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Dvideo.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <media/v4l2-event.h>
21 tegra_channels_cleanup(vid->vi); in tegra_v4l2_dev_release()
24 media_device_unregister(&vid->media_dev); in tegra_v4l2_dev_release()
25 media_device_cleanup(&vid->media_dev); in tegra_v4l2_dev_release()
39 v4l2_event_queue(&chan->video, arg); in tegra_v4l2_dev_notify()
40 if (ev->type == V4L2_EVENT_SOURCE_CHANGE && vb2_is_streaming(&chan->queue)) in tegra_v4l2_dev_notify()
41 vb2_queue_error(&chan->queue); in tegra_v4l2_dev_notify()
51 return -ENOMEM; in host1x_video_probe()
53 dev_set_drvdata(&dev->dev, vid); in host1x_video_probe()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 tegra-video-objs := \
6 csi.o
8 tegra-video-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
9 tegra-video-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
10 obj-$(CONFIG_VIDEO_TEGRA) += tegra-video.o
Dcsi.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <media/v4l2-fwnode.h>
18 #include "csi.h"
35 * CSI is a separate subdevice which has 6 source pads to generate
36 * test pattern. CSI subdevice pad ops are used only for TPG and
70 return -ENOIOCTLCMD; in csi_enum_bus_code()
72 if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) in csi_enum_bus_code()
73 return -EINVAL; in csi_enum_bus_code()
75 code->code = tegra_csi_tpg_fmts[code->index].code; in csi_enum_bus_code()
87 return -ENOIOCTLCMD; in csi_get_format()
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Dvi.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <media/v4l2-dv-timings.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-fh.h>
24 #include <media/v4l2-fwnode.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/videobuf2-dma-contig.h>
36 * struct tegra_vi_graph_entity - Entity in the video graph
72 for (i = offset; i < vi->soc->nformats; ++i) { in tegra_get_format_idx_by_code()
73 if (vi->soc->video_formats[i].code == code) in tegra_get_format_idx_by_code()
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/linux-6.12.1/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra210-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra CSI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^csi@[0-9a-f]+$"
19 - nvidia,tegra210-csi
26 - description: module clock
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Dnvidia,tegra20-vi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^vi@[0-9a-f]+$"
19 - const: nvidia,tegra20-vi
20 - const: nvidia,tegra30-vi
21 - const: nvidia,tegra114-vi
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Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
19 - enum:
20 - nvidia,tegra20-host1x
21 - nvidia,tegra30-host1x
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Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
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/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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Dtegra210-p2371-2180.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra210-p2180.dtsi"
5 #include "tegra210-p2597.dtsi"
9 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
14 hvddio-pex-supply = <&vdd_1v8>;
15 dvddio-pex-supply = <&vdd_pex_1v05>;
16 vddio-pex-ctl-supply = <&vdd_1v8>;
19 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
20 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
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Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
8 #include "tegra210.dtsi"
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
33 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_1v05>;
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Dtegra210-p2597.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 model = "NVIDIA Tegra210 P2597 I/O board";
9 compatible = "nvidia,p2597", "nvidia,tegra210";
23 avdd-dsi-csi-supply = <&vdd_dsi_csi>;
25 csi@838 {
33 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
34 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
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Dtegra210-smaug.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/mfd/max77620.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include "tegra210.dtsi"
12 compatible = "google,smaug-rev8", "google,smaug-rev7",
13 "google,smaug-rev6", "google,smaug-rev5",
14 "google,smaug-rev4", "google,smaug-rev3",
15 "google,smaug-rev2", "google,smaug-rev1",
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/linux-6.12.1/drivers/spi/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
17 obj-$(CONFIG_SPI_AIROHA_SNFI) += spi-airoha-snfi.o
18 obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
155 supports spi-mem interface.
234 this code to manage the per-word or per-transfer accesses to the
264 Flash over 1/2/4-bit wide bus. Enable this option if you have a
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/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
787 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
791 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
873 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
877 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
881 data->periph.gate.regs = bank; in periph_clk_init()
899 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in gate_clk_init()
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/linux-6.12.1/drivers/gpu/drm/tegra/
Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
30 #include "mipi-phy.h"
81 /* for ganged-mode support */
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
119 trace_dsi_writel(dsi->dev, offset, value); in tegra_dsi_writel()
120 writel(value, dsi->regs + (offset << 2)); in tegra_dsi_writel()
201 struct drm_info_node *node = s->private; in tegra_dsi_show_regs()
202 struct tegra_dsi *dsi = node->info_ent->data; in tegra_dsi_show_regs()
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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