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Searched +full:tegra20 +full:- +full:sflash (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dnvidia,tegra20-sflash.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra20-sflash.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SFLASH controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-sflash
25 - description: module clock
29 - description: module reset
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/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra20-pinmux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 Pinmux Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-pinmux
19 - description: tri-state registers
20 - description: mux register
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/linux-6.12.1/drivers/spi/
Dspi-tegra20-sflash.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI driver for Nvidia's Tegra20 Serial Flash Controller.
91 #define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF)
142 return readl(tsd->base + reg); in tegra_sflash_readl()
148 writel(val, tsd->base + reg); in tegra_sflash_writel()
161 unsigned remain_len = t->len - tsd->cur_pos; in tegra_sflash_calculate_curr_xfer_param()
164 tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8); in tegra_sflash_calculate_curr_xfer_param()
165 max_word = remain_len / tsd->bytes_per_word; in tegra_sflash_calculate_curr_xfer_param()
168 tsd->curr_xfer_words = max_word; in tegra_sflash_calculate_curr_xfer_param()
177 unsigned max_n_32bit = tsd->curr_xfer_words; in tegra_sflash_fill_tx_fifo_from_client_txbuf()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
17 obj-$(CONFIG_SPI_AIROHA_SNFI) += spi-airoha-snfi.o
18 obj-$(CONFIG_SPI_ALTERA) += spi-altera-platform.o
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/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra20-trimslice.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include "tegra20.dtsi"
7 #include "tegra20-cpu-opp.dtsi"
11 compatible = "compulab,trimslice", "nvidia,tegra20";
20 stdout-path = "serial0:115200n8";
31 vdd-supply = <&hdmi_vdd_reg>;
32 pll-supply = <&hdmi_pll_reg>;
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Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
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Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
6 #include "tegra20.dtsi"
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
11 model = "NVIDIA Tegra20 Ventana evaluation board";
12 compatible = "nvidia,ventana", "nvidia,tegra20";
21 stdout-path = "serial0:115200n8";
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Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20.dtsi"
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
15 compatible = "acer,picasso", "nvidia,tegra20";
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Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20.dtsi"
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
15 compatible = "asus,tf101", "nvidia,tegra20";
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Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20.dtsi"
9 compatible = "nvidia,seaboard", "nvidia,tegra20";
18 stdout-path = "serial0:115200n8";
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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/linux-6.12.1/drivers/pinctrl/tegra/
Dpinctrl-tegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pinctrl data for the NVIDIA Tegra20 pinmux
7 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
14 #include <linux/clk-provider.h>
21 #include "pinctrl-tegra.h"
254 /* All non-GPIO pins follow */
1942 FUNCTION(sflash),
1967 /* Pin group with mux control, and typically tri-state and pull-up/down too */
1980 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
1983 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
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