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/linux-6.12.1/Documentation/arch/riscv/
Dcmodx.rst9 (icache) are not guaranteed to be synchronized on RISC-V hardware. Therefore, the
15 migration occurs after the userspace synchronized the icache and instruction
18 Thus, the hart that the task has been migrated to may not have synchronized
/linux-6.12.1/Documentation/devicetree/bindings/hsi/
Dclient-devices.txt15 - hsi-flow: RX flow type ("synchronized" or "pipeline")
38 hsi-flow = "synchronized";
Dnokia-modem.txt43 hsi-flow = "synchronized";
/linux-6.12.1/sound/firewire/fireface/
Dff-protocol-latter.c32 // 0x00000040: Synchronized to word clock on BNC interface
33 // 0x00000020: Synchronized to ADAT or S/PDIF on optical interface
34 // 0x00000010: Synchronized to S/PDIF on coaxial interface
52 // 0x00000080: Synchronized to ADAT-B on 2nd optical interface
53 // 0x00000040: Synchronized to ADAT-A on 1st optical interface
54 // 0x00000020: Synchronized to AES/EBU on XLR or 2nd optical interface
55 // 0x00000010: Synchronized to word clock on BNC interface
/linux-6.12.1/drivers/comedi/drivers/
Dadv_pci1720.c27 * The analog outputs can operate in two modes, immediate and synchronized.
28 * This driver currently does not support the synchronized output mode.
149 /* disable synchronized output, channels update when written */ in pci1720_auto_attach()
/linux-6.12.1/include/uapi/linux/
Ddma-buf.h146 * synchronized APIs such as Vulkan to inter-op with dma-buf consumers
158 * implicitly synchronized writes to this dma-buf will wait on this
162 * write fence. All subsequent implicitly synchronized access to
Dtimex.h198 #define TIME_OK 0 /* clock synchronized, no leap second */
203 #define TIME_ERROR 5 /* clock not synchronized */
/linux-6.12.1/Documentation/devicetree/bindings/timer/
Drenesas,rz-mtu3.yaml43 complementary PWM and reset-synchronized PWM operation
52 reset-synchronized PWM output is settable and allows the selection
70 to be started with any desired timing and to be synchronized with
87 The module supports PWM mode{1,2}, Reset-synchronized PWM mode and
/linux-6.12.1/arch/arm/mach-omap2/
Ddma.c101 * a. Channel i, hardware synchronized, is enabled in configure_dma_errata()
102 * b. Another channel (Channel x), software synchronized, is enabled. in configure_dma_errata()
106 * f. A third channel (Channel y), software synchronized, is enabled. in configure_dma_errata()
/linux-6.12.1/sound/soc/sh/rcar/
Dssiu.c181 * set synchronized bit here in rsnd_ssiu_init()
184 /* SSI4 is synchronized with SSI3 */ in rsnd_ssiu_init()
187 /* SSI012 are synchronized */ in rsnd_ssiu_init()
190 /* SSI0129 are synchronized */ in rsnd_ssiu_init()
/linux-6.12.1/include/linux/
Dpvclock_gtod.h9 * and is used to keep guest time synchronized with host time.
/linux-6.12.1/Documentation/virt/kvm/x86/
Dtimekeeping.rst347 determine offset information in SMP systems where TSCs are not synchronized.
370 practice, getting a perfectly synchronized TSC will not be possible unless all
378 may not have a TSC value that is synchronized with the rest of the system.
382 TSC is synchronized back to a state where TSC synchronization flaws, however
401 It is recommended not to trust the TSCs to remain synchronized on NUMA or
493 synchronized with real time.
551 the TSC as seen from other CPUs, even in an otherwise perfectly synchronized
Dmmu.rst262 are synchronized when the guest executes invlpg or flushes its tlb by
278 emulations if the page needs to be write-protected (see "Synchronized
296 Synchronized and unsynchronized pages
330 - synchronized shadow pages are write protected (*)
/linux-6.12.1/net/core/
Ddev_addr_lists.c415 * __hw_addr_ref_unsync_dev - Remove synchronized addresses and references on
417 * @list: address list to remove synchronized addresses (references on it) from
451 * __hw_addr_unsync_dev - Remove synchronized addresses from device
452 * @list: address list to remove synchronized addresses from
780 * dev_uc_unsync - Remove synchronized addresses from the destination device
1003 * dev_mc_unsync - Remove synchronized addresses from the destination device
/linux-6.12.1/tools/testing/selftests/drivers/net/ocelot/
Dpsfp.sh182 # Set up swp1 as a master PHC for h1, synchronized to the local
187 # synchronizing h1 to swp1 via PTP, h2 is also implicitly synchronized
/linux-6.12.1/arch/x86/include/asm/
Dtsc.h49 * Boot-time check whether the TSCs are synchronized across
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dawinic,aw88395.yaml43 Flag bit used to keep the phase synchronized in the case of multiple PA
/linux-6.12.1/Documentation/driver-api/
Dpps.rst77 synchronized with PPS through USB. With USB 2.0, jitter may decrease
203 computers' clock to be synchronized very tightly.
/linux-6.12.1/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-orangepi-lite2.dts43 * Before the kernel can support synchronized
/linux-6.12.1/security/selinux/include/
Dsecurity.h112 /* do a synchronized load to avoid race conditions */ in selinux_initialized()
118 /* do a synchronized write to avoid race conditions */ in selinux_mark_initialized()
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_cdclk.h48 /* pipe to which cd2x update is synchronized */
/linux-6.12.1/Documentation/networking/
Dipvs-sysctl.rst227 the connection will be synchronized. A connection will be
228 synchronized, every time the number of its incoming packets
/linux-6.12.1/drivers/scsi/bfa/
Dbfa_ioc_cb.c213 * Synchronized IOC failure processing routines
252 * Synchronized IOC failure processing routines
/linux-6.12.1/rust/kernel/block/mq/
Drequest.rs187 // synchronized.
191 // mutate `self` are internally synchronized`
/linux-6.12.1/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.yaml16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-

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