Home
last modified time | relevance | path

Searched +full:sync +full:- +full:active (Results 1 – 25 of 1026) sorted by relevance

12345678910>>...42

/linux-6.12.1/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
15 # Sync Width 3.813 us 0.064 ms
21 # Active Time 25.422 us 15.253 ms
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
40 # Sync Width 2.032 us 0.080 ms
46 # Active Time 20.317 us 12.800 ms
52 mode "640x480-75"
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
[all …]
Dep93xx-fb.rst24 Note that the pixel clock value is in pico-seconds. You can use the
58 EP93XXFB_SYNC_BLANK_HIGH Blank signal is active high. By
59 default the blank signal is active low.
61 EP93XXFB_SYNC_HORIZ_HIGH Horizontal sync is active high. By
62 default the horizontal sync is active low.
64 EP93XXFB_SYNC_VERT_HIGH Vertical sync is active high. By
65 default the vertical sync is active high.
98 struct ep93xxfb_mach_info *mach_info = pdev->dev.platform_data;
110 video=XRESxYRES[-BPP][@REFRESH]
112 If the EP93xx video driver is built-in then the video mode is set on
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/panel/
Dpanel-timing.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
[all …]
/linux-6.12.1/include/video/
Ddisplay_timing.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 /* drive sync on pos. edge */
32 /* drive sync on neg. edge */
52 * Example: hsync active high, vsync active low
54 * Active Video
56 * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync..
66 struct timing_entry hactive; /* hor. active video */
69 struct timing_entry hsync_len; /* hor. sync len */
71 struct timing_entry vactive; /* ver. active video */
74 struct timing_entry vsync_len; /* ver. sync len */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Dtvp7002.txt7 - compatible : Must be "ti,tvp7002"
10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
16 - pclk-sample: Clock polarity of the bus. Default value when this property is
19 - sync-on-green-active: Active state of Sync-on-green signal property of the
21 0 = Normal Operation (Active Low, Default)
24 - field-even-active: Active-high Field ID output polarity control of the bus.
27 0 = Normal Operation (Active Low, Default)
31 video-interfaces.txt.
44 hsync-active = <1>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
/linux-6.12.1/drivers/net/wireless/intel/iwlwifi/mvm/
Dtime-sync.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
7 #include "time-sync.h"
12 skb_queue_head_init(&data->frame_list); in iwl_mvm_init_time_sync()
17 struct ieee80211_mgmt *mgmt = (void *)skb->data; in iwl_mvm_is_skb_match()
21 skb_dialog_token = mgmt->u.action.u.wnm_timing_msr.dialog_token; in iwl_mvm_is_skb_match()
23 skb_dialog_token = mgmt->u.action.u.ftm.dialog_token; in iwl_mvm_is_skb_match()
25 if ((ether_addr_equal(mgmt->sa, addr) || in iwl_mvm_is_skb_match()
26 ether_addr_equal(mgmt->da, addr)) && in iwl_mvm_is_skb_match()
39 * in the queue, they did not get a time sync notification and are in iwl_mvm_time_sync_find_skb()
42 while ((skb = skb_dequeue(&mvm->time_sync.frame_list))) { in iwl_mvm_time_sync_find_skb()
[all …]
/linux-6.12.1/include/drm/
Ddrm_modes.h3 * Copyright © 2007-2008 Dave Airlie
4 * Copyright © 2007-2008 Intel Corporation
46 * enum drm_mode_status - hardware support status of a mode
68 * @MODE_HSYNC_NARROW: horizontal sync too narrow
69 * @MODE_HSYNC_WIDE: horizontal sync too wide
72 * @MODE_VSYNC_NARROW: vertical sync too narrow
73 * @MODE_VSYNC_WIDE: vertical sync too wide
129 MODE_STALE = -3,
130 MODE_BAD = -2,
131 MODE_ERROR = -1
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/tilcdc/
Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
/linux-6.12.1/drivers/accel/habanalabs/common/
Dstate_dump.c1 // SPDX-License-Identifier: GPL-2.0
13 * hl_format_as_binary - helper function, format an integer as binary
37 buf_len -= 3; in hl_format_as_binary()
43 bit = n & (1 << (sizeof(n) * BITS_PER_BYTE - 1)); in hl_format_as_binary()
58 * resize_to_fit - helper function, resize buffer to fit given amount of data
79 return -ENOMEM; in resize_to_fit()
89 * hl_snprintf_resize() - print formatted data to buffer, resize as needed
113 return -EINVAL; in hl_snprintf_resize()
116 length = vsnprintf(*buf + *offset, *size - *offset, format, args); in hl_snprintf_resize()
125 length = vsnprintf(*buf + *offset, *size - *offset, format, in hl_snprintf_resize()
[all …]
/linux-6.12.1/drivers/dma-buf/
Dsync_debug.h2 * Sync File validation framework and debug infomation
19 #include <linux/dma-fence.h>
25 * struct sync_timeline - sync object
29 * @pt_tree: rbtree of active (unsignaled/errored) sync_pts
30 * @pt_list: list of active (unsignaled/errored) sync_pts
50 return container_of(fence->lock, struct sync_timeline, lock); in dma_fence_parent()
54 * struct sync_pt - sync_pt object
56 * @link: link on the sync timeline's list
57 * @node: node in the sync timeline's tree
/linux-6.12.1/drivers/gpu/drm/mcde/
Dmcde_display_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
236 #define MCDE_TVBL1_BSL1_SHIFT 16 /* VSW vertical sync pulse width 11 bits */
253 * 0 = 1 pixel HBP, 255 = 256 pixels, so actual value - 1
262 #define MCDE_TVLBALW_LBW_SHIFT 0 /* HSW horizonal sync width, line blanking width 11 bits */
263 #define MCDE_TVLBALW_ALW_SHIFT 16 /* HFP horizontal front porch, active line width 11 bits */
281 /* inverted vertical sync pulse for HRTFT 0 = active low, 1 active high */
283 /* inverted vertical sync, 0 = active high (the normal), 1 = active low */
285 /* inverted horizontal sync, 0 = active high (the normal), 1 = active low */
289 /* invert output enable 0 = active high, 1 = active low */
333 #define MCDE_VSCRC_VSPOL BIT(27) /* 0 active high, 1 active low */
[all …]
/linux-6.12.1/tools/testing/selftests/sync/
Dsync_wait.c2 * sync fence wait tests
3 * Copyright 2015-2016 Collabora Ltd.
28 #include "sync.h"
36 int valid, active, signaled, ret; in test_fence_multi_timeline_wait() local
53 active = sync_fence_count_with_status(merged, FENCE_STATUS_ACTIVE); in test_fence_multi_timeline_wait()
54 ASSERT(active == 3, "Fence signaled too early!\n"); in test_fence_multi_timeline_wait()
61 active = sync_fence_count_with_status(merged, FENCE_STATUS_ACTIVE); in test_fence_multi_timeline_wait()
63 ASSERT(active == 2 && signaled == 1, in test_fence_multi_timeline_wait()
67 active = sync_fence_count_with_status(merged, FENCE_STATUS_ACTIVE); in test_fence_multi_timeline_wait()
69 ASSERT(active == 1 && signaled == 2, in test_fence_multi_timeline_wait()
[all …]
Dsync_fence.c2 * sync fence tests with one timeline
3 * Copyright 2015-2016 Collabora Ltd.
28 #include "sync.h"
48 /* Advance timeline from 0 -> 1 */ in test_fence_one_timeline_wait()
96 /* confirm all fences have one active point (even d) */ in test_fence_one_timeline_merge()
98 "a has too many active fences!\n"); in test_fence_one_timeline_merge()
100 "b has too many active fences!\n"); in test_fence_one_timeline_merge()
102 "c has too many active fences!\n"); in test_fence_one_timeline_merge()
104 "d has too many active fences!\n"); in test_fence_one_timeline_merge()
/linux-6.12.1/include/uapi/linux/
Dnet_tstamp.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
38 SOF_TIMESTAMPING_MASK = (SOF_TIMESTAMPING_LAST - 1) |
53 * struct so_timestamping - SO_TIMESTAMPING parameter
65 * struct hwtstamp_config - %SIOCGHWTSTAMP and %SIOCSHWTSTAMP parameter
83 /* possible values for hwtstamp_config->flags */
86 * With this flag, the user could get bond active interface's
88 * is a failover, the bond active interface will be changed, so
95 HWTSTAMP_FLAG_MASK = (HWTSTAMP_FLAG_LAST - 1) | HWTSTAMP_FLAG_LAST
98 /* possible values for hwtstamp_config->tx_type */
118 * directly into Sync packets. In this case, transmitted Sync
[all …]
Dip_vs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
23 #define IP_VS_SVC_F_ONEPACKET 0x0004 /* one-packet scheduling */
38 * IPVS sync daemon states
88 #define IP_VS_CONN_F_SYNC 0x0020 /* entry created by sync */
168 /* thresholds for active connections */
236 __u32 activeconns; /* active connections */
281 /* sync daemon state (master/backup) */
321 IPVS_CMD_NEW_DAEMON, /* start sync daemon */
322 IPVS_CMD_DEL_DAEMON, /* stop sync daemon */
323 IPVS_CMD_GET_DAEMON, /* get sync daemon status */
[all …]
/linux-6.12.1/drivers/net/wireless/ralink/rt2x00/
Drt2x00config.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
31 conf.sync = TSF_SYNC_ADHOC; in rt2x00lib_config_intf()
35 conf.sync = TSF_SYNC_AP_NONE; in rt2x00lib_config_intf()
38 conf.sync = TSF_SYNC_INFRA; in rt2x00lib_config_intf()
41 conf.sync = TSF_SYNC_NONE; in rt2x00lib_config_intf()
60 if (mac || (!rt2x00dev->intf_ap_count && !rt2x00dev->intf_sta_count)) in rt2x00lib_config_intf()
62 if (bssid || (!rt2x00dev->intf_ap_count && !rt2x00dev->intf_sta_count)) in rt2x00lib_config_intf()
65 rt2x00dev->ops->lib->config_intf(rt2x00dev, intf, &conf, flags); in rt2x00lib_config_intf()
79 erp.short_preamble = bss_conf->use_short_preamble; in rt2x00lib_config_erp()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/
Drenesas,drif.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
[all …]
/linux-6.12.1/drivers/media/i2c/
Dths8200.c2 * ths8200 - Texas Instruments THS8200 video encoder driver
23 #include <linux/v4l2-dv-timings.h>
25 #include <media/v4l2-dv-timings.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-device.h>
33 MODULE_PARM_DESC(debug, "debug level (0-2)");
93 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
94 * and then the value-mask (to be OR-ed).
108 reg->val = ths8200_read(sd, reg->reg & 0xff); in ths8200_g_register()
109 reg->size = 1; in ths8200_g_register()
[all …]
/linux-6.12.1/drivers/md/
Dmd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 Copyright (C) 1996-98 Ingo Molnar, Gadi Oxman
12 #include <linux/backing-dev.h>
22 #include "md-cluster.h"
37 /* Status of sync thread. */
41 * 1) after assemble, sync data from first rdev to other copies, this
42 * must be done first before other sync actions and will only execute
44 * 2) resize the array(notice that this is not reshape), sync data for
50 * 1) for new replacement, sync data based on the replace rdev or
52 * 2) for new member disk while the array is degraded, sync data from
[all …]
/linux-6.12.1/sound/soc/ti/
Ddavinci-i2s.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * based on davinci-mcasp.c DT support
30 #include "edma-pcm.h"
31 #include "davinci-i2s.h"
33 #define DRV_NAME "davinci-i2s"
38 * - This driver supports the "Audio Serial Port" (ASP),
41 * - But it labels it a "Multi-channel Buffered Serial Port"
43 * backward-compatible, possibly explaining that confusion.
45 * - OMAP chips have a controller called McBSP, which is
48 * - Newer DaVinci chips have a controller called McASP,
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice_dpll.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /** ice_dpll_pin - store info about pins
37 /** ice_dpll - store info required for DPLL control
45 * @phase_offset: phase offset of active pin vs dpll signal
46 * @prev_phase_offset: previous phase offset of active pin vs dpll signal
48 * @dpll_state: current dpll sync state
49 * @prev_dpll_state: last dpll sync state
50 * @active_input: pointer to active input pin
51 * @prev_input: pointer to previous active input pin
71 /** ice_dplls - store info required for CCU (clock controlling unit)
/linux-6.12.1/drivers/gpu/drm/bridge/analogix/
Danalogix-i2c-txcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
104 /* Active Line Status Low Byte Register */
107 /* Active Line Status High Byte Register */
113 /* Vertical SYNC Width Status Register */
125 /* Active Pixel Status Low Byte Register */
128 /* Active Pixel Status High Byte Register */
137 /* Horizontal SYNC Width Status Low Byte Register */
140 /* Horizontal SYNC Width Status High Byte Register */
200 #define SP_COMMON_INT_STATUS_BASE (0xf1 - 1)
224 #define SP_COMMON_INT_MASK_BASE (0xf8 - 1)
/linux-6.12.1/arch/mips/cavium-octeon/executive/
Dcvmx-spi.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
98 * active) or as a halfplex (either the Tx data path is
[all …]
/linux-6.12.1/Documentation/userspace-api/media/v4l/
Dvidioc-g-dv-timings.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_G_DV_TIMINGS - VIDIOC_S_DV_TIMINGS - VIDIOC_SUBDEV_G_DV_TIMINGS - VIDIOC_SUBDEV_S_DV_TIMINGS…
56 registered in read-only mode is not allowed. An error is returned and the errno
57 variable is set to ``-EPERM``.
59 The ``linux/v4l2-dv-timings.h`` header can be used to get the timings of
68 On success 0 is returned, on error -1 and the ``errno`` variable is set
70 :ref:`Generic Error Codes <gen-errors>` chapter.
83 ``VIDIOC_SUBDEV_S_DV_TIMINGS`` has been called on a read-only subdevice.
91 .. flat-table:: struct v4l2_bt_timings
92 :header-rows: 0
[all …]

12345678910>>...42