Searched +full:sun9i +full:- +full:a80 +full:- +full:pll4 +full:- +full:clk (Results 1 – 8 of 8) sorted by relevance
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun9i-a80-pll4-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 Peripheral PLL
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun9i-a80-pll4-clk
28 clock-output-names:
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| D | allwinner,sun9i-a80-apb0-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-apb0-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 APB0 Bus Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
21 - allwinner,sun9i-a80-apb0-clk
22 - allwinner,sun9i-a80-apb1-clk
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| D | allwinner,sun9i-a80-cpus-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-cpus-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 CPUS Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun9i-a80-cpus-clk
30 clock-output-names:
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| D | allwinner,sun9i-a80-gt-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-gt-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 GT Bus Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun9i-a80-gt-clk
30 clock-output-names:
[all …]
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| D | allwinner,sun9i-a80-ahb-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 AHB Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun9i-a80-ahb-clk
30 clock-output-names:
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| D | allwinner,sun4i-a10-mmc-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mmc-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
25 - allwinner,sun4i-a10-mmc-clk
26 - allwinner,sun9i-a80-mmc-clk
37 clock-output-names:
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| /linux-6.12.1/drivers/clk/sunxi/ |
| D | clk-sun9i-core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include "clk-factors.h"
18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
19 * PLL4 rate is calculated as follows
33 n = DIV_ROUND_UP(req->rate, 6000000); in sun9i_a80_get_pll4_factors()
53 req->rate = ((24000000 * n) >> p) / (m + 1); in sun9i_a80_get_pll4_factors()
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| D | clk-sun9i-cpus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Allwinner A80 CPUS clock driver
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
57 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
59 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
63 /* clk divider */ in sun9i_a80_cpus_clk_recalc_rate()
83 /* calculate pre-divider if parent is pll4 */ in sun9i_a80_cpus_clk_round()
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