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/linux-6.12.1/Documentation/devicetree/bindings/soc/starfive/
Dstarfive,jh7110-syscon.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Qiu <william.qiu@starfivetech.com>
19 - items:
20 - const: starfive,jh7110-sys-syscon
21 - const: syscon
22 - const: simple-mfd
23 - items:
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/linux-6.12.1/Documentation/devicetree/bindings/usb/
Dstarfive,jh7110-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb
18 starfive,stg-syscon:
19 $ref: /schemas/types.yaml#/definitions/phandle-array
21 - items:
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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dstarfive,jh7110-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-pcie-phy
19 "#phy-cells":
22 starfive,sys-syscon:
23 $ref: /schemas/types.yaml#/definitions/phandle-array
25 - items:
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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dstarfive,jh7110-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kevin Xie <kevin.xie@starfivetech.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
17 const: starfive,jh7110-pcie
21 - description: NOC bus clock
22 - description: Transport layer clock
23 - description: AXI MST0 clock
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/linux-6.12.1/drivers/usb/cdns3/
Dcdns3-starfive.c1 // SPDX-License-Identifier: GPL-2.0
3 * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
13 #include <linux/mfd/syscon.h>
49 regmap_update_bits(data->stg_syscon, data->stg_usb_mode, in cdns_mode_init()
54 mode = usb_get_dr_mode(&pdev->dev); in cdns_mode_init()
58 regmap_update_bits(data->stg_syscon, in cdns_mode_init()
59 data->stg_usb_mode, in cdns_mode_init()
62 regmap_update_bits(data->stg_syscon, in cdns_mode_init()
63 data->stg_usb_mode, in cdns_mode_init()
69 regmap_update_bits(data->stg_syscon, data->stg_usb_mode, in cdns_mode_init()
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/linux-6.12.1/drivers/pci/controller/plda/
Dpcie-starfive.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <linux/mfd/syscon.h>
27 #include "pcie-plda.h"
67 * JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory
110 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); in starfive_pcie_parse_dt()
111 if (pcie->num_clks < 0) in starfive_pcie_parse_dt()
112 return dev_err_probe(dev, pcie->num_clks, in starfive_pcie_parse_dt()
115 pcie->resets = devm_reset_control_array_get_exclusive(dev); in starfive_pcie_parse_dt()
116 if (IS_ERR(pcie->resets)) in starfive_pcie_parse_dt()
117 return dev_err_probe(dev, PTR_ERR(pcie->resets), in starfive_pcie_parse_dt()
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/linux-6.12.1/drivers/phy/starfive/
Dphy-jh7110-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <linux/mfd/syscon.h>
49 if (!data->stg_syscon || !data->sys_syscon) { in phy_usb3_mode_set()
50 dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); in phy_usb3_mode_set()
51 return -EINVAL; in phy_usb3_mode_set()
54 regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, in phy_usb3_mode_set()
56 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
58 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
62 regmap_update_bits(data->sys_syscon, data->sys_phy_connect, in phy_usb3_mode_set()
65 /* Configuare spread-spectrum mode: down-spread-spectrum */ in phy_usb3_mode_set()
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/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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