| /linux-6.12.1/Documentation/devicetree/bindings/spi/ ! |
| D | brcm,spi-bcm-qspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
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| /linux-6.12.1/arch/arm/boot/dts/broadcom/ ! |
| D | bcm5301x.dtsi | 9 #include "bcm-ns.dtsi"
12 mpcore-bus@19000000 {
14 #clock-cells = <0>;
15 compatible = "brcm,nsp-armpll";
21 compatible = "arm,cortex-a9-twd-wdt";
30 #address-cells = <1>;
31 #size-cells = <1>;
35 #clock-cells = <0>;
36 compatible = "fixed-clock";
37 clock-frequency = <25000000>;
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| D | bcm958522er.dts | 33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
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| D | bcm-nsp.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "brcm,nsp";
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
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| D | bcm958525er.dts | 33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
81 nand-on-flash-bbt;
83 #address-cells = <1>;
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| D | bcm-hr2.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
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| D | bcm958622hr.dts | 33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
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| D | bcm958525xmc.dts | 33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
76 temperature-sensor@4c {
97 nand-on-flash-bbt;
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| D | bcm958625hr.dts | 33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
60 i2c-bus = <&i2c0>;
61 mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
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| D | bcm958623hr.dts | 33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
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| D | bcm988312hr.dts | 33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
36 #include <dt-bindings/gpio/gpio.h>
40 compatible = "brcm,bcm988312hr", "brcm,bcm88312", "brcm,nsp";
43 stdout-path = "serial0:115200n8";
51 gpio-restart {
52 compatible = "gpio-restart";
54 open-source;
85 nand-on-flash-bbt;
87 #address-cells = <1>;
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| D | bcm958625k.dts | 33 /dts-v1/;
35 #include "bcm-nsp.dtsi"
39 compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp";
42 stdout-path = "serial0:115200n8";
75 nand-on-flash-bbt;
77 #address-cells = <1>;
78 #size-cells = <1>;
80 nand-ecc-strength = <24>;
81 nand-ecc-step-size = <1024>;
83 brcm,nand-oob-sector-size = <27>;
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| /linux-6.12.1/drivers/spi/ ! |
| D | spi-iproc-qspi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "spi-bcm-qspi.h"
33 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_get_l2_int_status()
38 if (bcm_qspi_readl(priv->big_endian, mmio + (i * 4))) in bcm_iproc_qspi_get_l2_int_status()
58 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_int_ack()
64 bcm_qspi_writel(priv->big_endian, 1, mmio + (i * 4)); in bcm_iproc_qspi_int_ack()
73 void __iomem *mmio = priv->int_reg; in bcm_iproc_qspi_int_set()
78 spin_lock_irqsave(&priv->soclock, flags); in bcm_iproc_qspi_int_set()
80 val = bcm_qspi_readl(priv->big_endian, mmio); in bcm_iproc_qspi_int_set()
87 bcm_qspi_writel(priv->big_endian, val, mmio); in bcm_iproc_qspi_int_set()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
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| D | spi-bcm-qspi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
21 #include <linux/spi/spi.h>
22 #include <linux/mtd/spi-nor.h>
25 #include "spi-bcm-qspi.h"
171 * to TXRAM and RXRAM when used as 32-bit registers respectively
255 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
257 return qspi->bspi_mode; in has_bspi()
260 /* hardware supports spcr3 and fast baud-rate */
261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
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| /linux-6.12.1/arch/arm64/boot/dts/qcom/ ! |
| D | sc7280.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
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| /linux-6.12.1/ ! |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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