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Searched +full:spi +full:- +full:ns2 +full:- +full:qspi (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
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/linux-6.12.1/arch/arm64/boot/dts/broadcom/northstar2/
Dns2-svk.dts33 /dts-v1/;
35 #include "ns2.dtsi"
38 model = "Broadcom NS2 SVK";
39 compatible = "brcm,ns2-svk", "brcm,ns2";
49 stdout-path = "serial0:115200n8";
113 spi-max-frequency = <5000000>;
114 spi-cpha;
115 spi-cpol;
117 pl022,slave-tx-disable = <0>;
118 pl022,com-mode = <0>;
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Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
39 compatible = "brcm,ns2";
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
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Dns2-xmc.dts33 /dts-v1/;
35 #include "ns2.dtsi"
38 model = "Broadcom NS2 XMC";
39 compatible = "brcm,ns2-xmc", "brcm,ns2";
46 stdout-path = "serial0:115200n8";
70 gphy0: eth-phy@10 {
80 nand-ecc-mode = "hw";
81 nand-ecc-strength = <8>;
82 nand-ecc-step-size = <512>;
83 nand-bus-width = <16>;
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/linux-6.12.1/drivers/spi/
Dspi-iproc-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "spi-bcm-qspi.h"
33 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_get_l2_int_status()
38 if (bcm_qspi_readl(priv->big_endian, mmio + (i * 4))) in bcm_iproc_qspi_get_l2_int_status()
58 void __iomem *mmio = priv->int_status_reg; in bcm_iproc_qspi_int_ack()
64 bcm_qspi_writel(priv->big_endian, 1, mmio + (i * 4)); in bcm_iproc_qspi_int_ack()
73 void __iomem *mmio = priv->int_reg; in bcm_iproc_qspi_int_set()
78 spin_lock_irqsave(&priv->soclock, flags); in bcm_iproc_qspi_int_set()
80 val = bcm_qspi_readl(priv->big_endian, mmio); in bcm_iproc_qspi_int_set()
87 bcm_qspi_writel(priv->big_endian, val, mmio); in bcm_iproc_qspi_int_set()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # SPI driver configuration
5 menuconfig SPI config
6 bool "SPI support"
10 protocol. Chips that support SPI can have data transfer rates
12 controller and a chipselect. Most SPI slaves don't support
13 dynamic device discovery; some are even write-only or read-only.
15 SPI is widely used by microcontrollers to talk with sensors,
17 chips, analog to digital (and d-to-a) converters, and more.
18 MMC and SD cards can be accessed using SPI protocol; and for
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Dspi-bcm-qspi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
21 #include <linux/spi/spi.h>
22 #include <linux/mtd/spi-nor.h>
25 #include "spi-bcm-qspi.h"
171 * to TXRAM and RXRAM when used as 32-bit registers respectively
255 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
257 return qspi->bspi_mode; in has_bspi()
260 /* hardware supports spcr3 and fast baud-rate */
261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
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