| /linux-6.12.1/drivers/net/ethernet/qualcomm/emac/ |
| D | emac-sgmii.c | 5 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
16 #include "emac-sgmii.h"
90 /* Initialize the SGMII link between the internal and external PHYs. */
123 net_err_ratelimited("%s: failed to clear SGMII irq: status:0x%x bits:0x%x\n", in emac_sgmii_irq_clear()
160 /* The SGMII is capable of recovering from some decode in emac_sgmii_interrupt()
195 * SGMII in emac_sgmii_reset_prepare()
216 struct emac_sgmii *sgmii = &adpt->phy; in emac_sgmii_common_open() local
219 if (sgmii->irq) { in emac_sgmii_common_open()
224 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); in emac_sgmii_common_open()
226 ret = request_irq(sgmii->irq, emac_sgmii_interrupt, 0, in emac_sgmii_common_open()
[all …]
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| D | Makefile | 8 qcom-emac-objs := emac.o emac-mac.o emac-phy.o emac-sgmii.o emac-ethtool.o \
9 emac-sgmii-fsm9900.o emac-sgmii-qdf2432.o \
10 emac-sgmii-qdf2400.o
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| D | emac-sgmii-qdf2432.c | 5 /* Qualcomm Technologies, Inc. QDF2432 EMAC SGMII Controller driver.
19 /* SGMII digital lane registers */
44 /* SGMII digital lane register values */
172 /* SGMII lane-x init */ in emac_sgmii_init_qdf2432()
189 netdev_err(adpt->netdev, "SGMII failed to start\n"); in emac_sgmii_init_qdf2432()
198 /* Mask out all the SGMII Interrupt */ in emac_sgmii_init_qdf2432()
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| D | emac-sgmii-qdf2400.c | 5 /* Qualcomm Technologies, Inc. QDF2400 EMAC SGMII Controller driver.
19 /* SGMII digital lane registers */
46 /* SGMII digital lane register values */
185 /* SGMII lane-x init */ in emac_sgmii_init_qdf2400()
202 netdev_err(adpt->netdev, "SGMII failed to start\n"); in emac_sgmii_init_qdf2400()
211 /* Mask out all the SGMII Interrupt */ in emac_sgmii_init_qdf2400()
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| /linux-6.12.1/drivers/net/dsa/sja1105/ |
| D | Kconfig | 17 - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet)
18 - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)
19 - SJA1105R (Gen. 2, SGMII, No TT-Ethernet)
20 - SJA1105S (Gen. 2, SGMII, TT-Ethernet)
21 - SJA1110A (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 10 ports)
22 - SJA1110B (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 9 ports)
23 - SJA1110C (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 7 ports)
24 - SJA1110D (Gen. 3, SGMII, TT-Ethernet, no 100base-TX PHY, 7 ports)
|
| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | socfpga-dwmac.txt | 27 altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
29 This device node has additional phandle dependency, the sgmii converter:
32 - compatible : Should be altr,gmii-to-sgmii-2.0
38 compatible = "altr,gmii-to-sgmii-2.0";
55 phy-mode = "sgmii";
56 altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
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| D | qcom-emac.txt | 3 This network controller consists of two devices: a MAC and an SGMII
20 - compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".
61 compatible = "qcom,fsm9900-emac-sgmii";
107 compatible = "qcom,qdf2432-emac-sgmii";
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| /linux-6.12.1/drivers/net/pcs/ |
| D | pcs-mtk-lynxi.c | 3 /* A library for MediaTek SGMII circuit
17 /* SGMII subsystem config registers */
50 /* Register to reset SGMII design */
54 /* Register to set SGMII speed, ANA RG_ Control Signals III */
68 /* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
71 * SGMII modes
149 /* Reset SGMII PCS state */ in mtk_pcs_lynxi_config()
191 * prevents SGMII from working. The SGMII still shows link but no traffic in mtk_pcs_lynxi_config()
193 * taken from a good working state of the SGMII interface. in mtk_pcs_lynxi_config()
278 dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id, in mtk_pcs_lynxi_create()
[all …]
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| /linux-6.12.1/arch/mips/cavium-octeon/executive/ |
| D | cvmx-helper-sgmii.c | 29 * Functions for SGMII initialization, configuration,
45 * Perform initialization required only once for an SGMII port.
67 * interval. SGMII specifies a 1.6ms interval. in __cvmx_helper_sgmii_hardware_init_one_time()
78 /* SGMII */ in __cvmx_helper_sgmii_hardware_init_one_time()
89 * In SGMII PHY mode, tx_Config_Reg<D15:D0> is in __cvmx_helper_sgmii_hardware_init_one_time()
90 * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, in __cvmx_helper_sgmii_hardware_init_one_time()
158 cvmx_dprintf("SGMII%d: Timeout waiting for port %d " in __cvmx_helper_sgmii_hardware_init_link()
167 * sgmii negotiation starts. in __cvmx_helper_sgmii_hardware_init_link()
177 * that sgmii autonegotiation is complete. In MAC mode this in __cvmx_helper_sgmii_hardware_init_link()
185 /* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */ in __cvmx_helper_sgmii_hardware_init_link()
[all …]
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| /linux-6.12.1/Documentation/networking/dsa/ |
| D | sja1105.rst | 12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
19 - SJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
20 - SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1
54 SGMII no yes
420 4 xMII xMII SGMII
[all …]
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| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso | 13 phy-connection-type = "sgmii";
19 phy-connection-type = "sgmii";
25 phy-connection-type = "sgmii";
31 phy-connection-type = "sgmii";
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| D | fsl-ls1046a-qds.dts | 35 sgmii-s1-p1 = &sgmii_phy_s1_p1;
36 sgmii-s1-p2 = &sgmii_phy_s1_p2;
37 sgmii-s1-p3 = &sgmii_phy_s1_p3;
38 sgmii-s1-p4 = &sgmii_phy_s1_p4;
39 sgmii-s4-p1 = &sgmii_phy_s4_p1;
197 phy-connection-type = "sgmii";
202 phy-connection-type = "sgmii";
217 phy-connection-type = "sgmii";
222 phy-connection-type = "sgmii";
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| D | fsl-ls1028a-qds-9999.dtso | 40 phy-mode = "sgmii";
47 phy-mode = "sgmii";
54 phy-mode = "sgmii";
61 phy-mode = "sgmii";
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| D | fsl-lx2162a-clearfog.dts | 118 phy-connection-type = "sgmii";
125 phy-connection-type = "sgmii";
132 phy-connection-type = "sgmii";
139 phy-connection-type = "sgmii";
146 phy-connection-type = "sgmii";
153 phy-connection-type = "sgmii";
164 phy-connection-type = "sgmii";
171 phy-connection-type = "sgmii";
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| D | fsl-ls1043a-qds.dts | 27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
30 sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
179 phy-connection-type = "sgmii";
184 phy-connection-type = "sgmii";
199 phy-connection-type = "sgmii";
204 phy-connection-type = "sgmii";
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| D | fsl-ls1028a-qds-899b.dtso | 38 phy-mode = "sgmii";
47 phy-mode = "sgmii";
54 phy-mode = "sgmii";
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| /linux-6.12.1/Documentation/devicetree/bindings/net/dsa/ |
| D | qca8k.yaml | 85 qca,sgmii-rxclk-falling-edge:
89 the QCA8327 with CPU port 0 set to SGMII.
91 qca,sgmii-txclk-falling-edge:
96 qca,sgmii-enable-pll:
99 For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
101 the SGMII port will not initialize. When used on the QCA8337, revision 3
103 SGMII on the QCA8337, it is advised to set this unless a communication
285 phy-mode = "sgmii";
287 qca,sgmii-rxclk-falling-edge;
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| /linux-6.12.1/arch/powerpc/boot/dts/fsl/ |
| D | p5040ds.dts | 179 phy-connection-type = "sgmii";
183 phy-connection-type = "sgmii";
187 phy-connection-type = "sgmii";
191 phy-connection-type = "sgmii";
207 phy-connection-type = "sgmii";
211 phy-connection-type = "sgmii";
215 phy-connection-type = "sgmii";
219 phy-connection-type = "sgmii";
314 hydra_sg_slot2: sgmii-mdio@28 {
337 hydra_sg_slot3: sgmii-mdio@68 {
[all …]
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| D | t4240rdb.dts | 157 phy-connection-type = "sgmii";
162 phy-connection-type = "sgmii";
167 phy-connection-type = "sgmii";
172 phy-connection-type = "sgmii";
197 phy-connection-type = "sgmii";
202 phy-connection-type = "sgmii";
207 phy-connection-type = "sgmii";
212 phy-connection-type = "sgmii";
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | qcom,sa8775p-dwmac-sgmii-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml#
7 title: Qualcomm SerDes/SGMII ethernet PHY controller
18 const: qcom,sa8775p-dwmac-sgmii-phy
50 compatible = "qcom,sa8775p-dwmac-sgmii-phy";
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| /linux-6.12.1/arch/mips/boot/dts/cavium-octeon/ |
| D | octeon_68xx.dts | 74 cavium,qlm-trim = "4,sgmii";
83 cavium,qlm-trim = "4,sgmii";
92 cavium,qlm-trim = "4,sgmii";
101 cavium,qlm-trim = "4,sgmii";
118 cavium,qlm-trim = "0,sgmii";
127 cavium,qlm-trim = "0,sgmii";
136 cavium,qlm-trim = "0,sgmii";
145 cavium,qlm-trim = "0,sgmii";
162 cavium,qlm-trim = "2,sgmii";
171 cavium,qlm-trim = "2,sgmii";
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/broadcom/ |
| D | bcm958625-meraki-alamo.dtsi | 119 phy-mode = "sgmii";
120 qca,sgmii-enable-pll;
121 qca,sgmii-txclk-falling-edge;
197 phy-mode = "sgmii";
198 qca,sgmii-enable-pll;
199 qca,sgmii-txclk-falling-edge;
|
| /linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/ |
| D | stmmac_pcs.h | 16 /* PCS registers (AN/TBI/SGMII/RGMII) offsets */
30 #define GMAC_AN_CTRL_SGMRAL BIT(18) /* SGMII RAL Control */
48 * dwmac_pcs_isr - TBI, RTBI, or SGMII PHY ISR
82 * @srgmi_ral: to manage MAC-2-MAC SGMII connections.
86 * configure SGMII RAL.
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| /linux-6.12.1/arch/mips/include/asm/octeon/ |
| D | cvmx-helper-sgmii.h | 31 * Functions for SGMII initialization, configuration,
39 * Probe a SGMII interface and determine the number of ports
40 * connected to it. The SGMII interface should still be down after
51 * Bringup and enable a SGMII interface. After this call packet
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| /linux-6.12.1/arch/mips/boot/dts/mscc/ |
| D | ocelot_pcb120.dts | 98 phy-mode = "sgmii";
105 phy-mode = "sgmii";
112 phy-mode = "sgmii";
119 phy-mode = "sgmii";
|