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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn401/
Ddcn401_optc.h11 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
12 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
13 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
14 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
15 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
16 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
17 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
18 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
19 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
20 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn32/
Ddcn32_optc.h32 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
33 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
34 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
35 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
36 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
37 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
38 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
39 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
40 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
41 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_mmhubbub.h136 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
137 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
138 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
139 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
140 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
141 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
142 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
143 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
144 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
145 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn30/
Ddcn30_optc.h117 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
118 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
119 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
120 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
121 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
122 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
123 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
124 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
125 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
126 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn31/
Ddcn31_optc.h105 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
106 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
107 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
108 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
109 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
110 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
111 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
112 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
113 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
114 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn314/
Ddcn314_optc.h104 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
105 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
106 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
107 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
108 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
109 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
110 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
111 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
112 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
113 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/
Ddcn32_mmhubbub.h84 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
85 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
86 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
87 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
88 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
89 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
90 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
91 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
92 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
93 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/
Ddcn20_mmhubbub.h91 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
92 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
93 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
94 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
95 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
96 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
97 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
98 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
99 SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\
100 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
Ddcn30_mpc.h429 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
430 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
431 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
432 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
433 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
434 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
435 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
436 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
437 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
438 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn10/
Ddcn10_optc.h208 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
209 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
210 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
211 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
212 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
213 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
214 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
215 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
216 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
217 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
[all …]
/linux-6.12.1/arch/arm64/net/
Dbpf_jit.h19 #define A64_VARIANT(sf) \ argument
20 ((sf) ? AARCH64_INSN_VARIANT_64BIT : AARCH64_INSN_VARIANT_32BIT)
23 #define A64_COMP_BRANCH(sf, Rt, offset, type) \ argument
24 aarch64_insn_gen_comp_branch_imm(0, offset, Rt, A64_VARIANT(sf), \
26 #define A64_CBZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, ZERO) argument
27 #define A64_CBNZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, NONZERO) argument
106 #define A64_SIZE(sf) \ argument
107 ((sf) ? AARCH64_INSN_SIZE_64 : AARCH64_INSN_SIZE_32)
108 #define A64_LSX(sf, Rt, Rn, Rs, type) \ argument
109 aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
Ddcn32_mpc.h180 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
181 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
182 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
183 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
184 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
185 SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL, mask_sh),\
186 SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT, mask_sh),\
187 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
188 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
189 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/sf/
Ddevlink.c7 #include "sf/dev/dev.h"
33 struct mutex sf_state_lock; /* Serializes sf state among user cmds & vhca event handler. */
45 static int mlx5_sf_function_id_insert(struct mlx5_sf_table *table, struct mlx5_sf *sf) in mlx5_sf_function_id_insert() argument
47 return xa_insert(&table->function_ids, sf->hw_fn_id, sf, GFP_KERNEL); in mlx5_sf_function_id_insert()
50 static void mlx5_sf_function_id_erase(struct mlx5_sf_table *table, struct mlx5_sf *sf) in mlx5_sf_function_id_erase() argument
52 xa_erase(&table->function_ids, sf->hw_fn_id); in mlx5_sf_function_id_erase()
60 struct mlx5_sf *sf; in mlx5_sf_alloc() local
76 sf = kzalloc(sizeof(*sf), GFP_KERNEL); in mlx5_sf_alloc()
77 if (!sf) { in mlx5_sf_alloc()
81 sf->id = id_err; in mlx5_sf_alloc()
[all …]
/linux-6.12.1/drivers/isdn/hardware/mISDN/
Dspeedfax.c115 struct sfax_hw *sf = dev_id; in IOFUNC_IND() local
119 spin_lock(&sf->lock); in IOFUNC_IND()
120 val = inb(sf->cfg + TIGER_AUX_STATUS); in IOFUNC_IND()
122 spin_unlock(&sf->lock); in IOFUNC_IND()
125 sf->irqcnt++; in IOFUNC_IND()
126 val = ReadISAR_IND(sf, ISAR_IRQBIT); in IOFUNC_IND()
129 mISDNisar_irq(&sf->isar); in IOFUNC_IND()
130 val = ReadISAC_IND(sf, ISAC_ISTA); in IOFUNC_IND()
132 mISDNisac_irq(&sf->isac, val); in IOFUNC_IND()
133 val = ReadISAR_IND(sf, ISAR_IRQBIT); in IOFUNC_IND()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dwb.h47 #define SF(reg_name, field_name, post_fix)\ macro
85 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
86 SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
87 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
88 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
89 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
90 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
91 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
92 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
93 SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn35/
Ddcn35_optc.h34 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_WINDOW_DB_EN, mask_sh),\
35 SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
36 SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
37 SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
38 SF(OTG0_OTG_CRC2_DATA_RG, CRC2_R_CR, mask_sh),\
39 SF(OTG0_OTG_CRC2_DATA_RG, CRC2_G_Y, mask_sh),\
40 SF(OTG0_OTG_CRC2_DATA_B, CRC2_B_CB, mask_sh),\
41 SF(OTG0_OTG_CRC3_DATA_RG, CRC3_R_CR, mask_sh),\
42 SF(OTG0_OTG_CRC3_DATA_RG, CRC3_G_Y, mask_sh),\
43 SF(OTG0_OTG_CRC3_DATA_B, CRC3_B_CB, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn20/
Ddcn20_optc.h50 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
51 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
52 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
53 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
54 SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
55 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
56 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
57 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
58 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
59 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn20/
Ddcn20_mpc.h138 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
139 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
140 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
141 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
142 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
143 SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
144 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
145 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
146 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
147 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
[all …]
/linux-6.12.1/arch/sparc/kernel/
Dsignal_32.c77 struct signal_frame __user *sf; in do_sigreturn() local
88 sf = (struct signal_frame __user *) regs->u_regs[UREG_FP]; in do_sigreturn()
91 if (invalid_frame_pointer(sf, sizeof(*sf))) in do_sigreturn()
94 if (get_user(ufp, &sf->info.si_regs.u_regs[UREG_FP])) in do_sigreturn()
100 err = __get_user(pc, &sf->info.si_regs.pc); in do_sigreturn()
101 err |= __get_user(npc, &sf->info.si_regs.npc); in do_sigreturn()
108 err |= __copy_from_user(regs, &sf->info.si_regs, sizeof(struct pt_regs)); in do_sigreturn()
117 err |= __get_user(fpu_save, &sf->fpu_save); in do_sigreturn()
120 err |= __get_user(rwin_save, &sf->rwin_save); in do_sigreturn()
127 err |= __get_user(set.sig[0], &sf->info.si_mask); in do_sigreturn()
[all …]
Dsignal32.c85 struct signal_frame32 __user *sf; in do_sigreturn32() local
100 sf = (struct signal_frame32 __user *) regs->u_regs[UREG_FP]; in do_sigreturn32()
103 if (invalid_frame_pointer(sf, sizeof(*sf))) in do_sigreturn32()
106 if (get_user(ufp, &sf->info.si_regs.u_regs[UREG_FP])) in do_sigreturn32()
112 if (__get_user(pc, &sf->info.si_regs.pc) || in do_sigreturn32()
113 __get_user(npc, &sf->info.si_regs.npc)) in do_sigreturn32()
127 err = __get_user(regs->y, &sf->info.si_regs.y); in do_sigreturn32()
128 err |= __get_user(psr, &sf->info.si_regs.psr); in do_sigreturn32()
131 err |= __get_user(regs->u_regs[i], &sf->info.si_regs.u_regs[i]); in do_sigreturn32()
133 err |= __get_user(i, &sf->v8plus.g_upper[0]); in do_sigreturn32()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn201/
Ddcn201_optc.h46 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
47 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
48 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
49 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
50 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
51 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
52 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
53 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
54 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
55 SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
[all …]
/linux-6.12.1/drivers/media/cec/core/
Dcec-pin-error-inj.c240 static void cec_pin_show_cmd(struct seq_file *sf, u32 cmd, u8 mode) in cec_pin_show_cmd() argument
243 seq_puts(sf, "any,"); in cec_pin_show_cmd()
245 seq_printf(sf, "0x%02x,", cmd); in cec_pin_show_cmd()
248 seq_puts(sf, "once "); in cec_pin_show_cmd()
251 seq_puts(sf, "always "); in cec_pin_show_cmd()
254 seq_puts(sf, "toggle "); in cec_pin_show_cmd()
257 seq_puts(sf, "off "); in cec_pin_show_cmd()
262 int cec_pin_error_inj_show(struct cec_adapter *adap, struct seq_file *sf) in cec_pin_error_inj_show() argument
267 seq_puts(sf, "# Clear error injections:\n"); in cec_pin_error_inj_show()
268 seq_puts(sf, "# clear clear all rx and tx error injections\n"); in cec_pin_error_inj_show()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
Ddcn401_mpc.h70 …SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, mask_…
71 SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mask_sh), \
72 SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mask_sh), \
73 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C11_A, mask_sh), \
74 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C12_A, mask_sh), \
75 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C13_A, mask_sh), \
76 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C14_A, mask_sh), \
77 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C21_A, mask_sh), \
78 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C22_A, mask_sh), \
79 SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C23_A, mask_sh), \
[all …]
/linux-6.12.1/drivers/gpu/drm/arm/display/komeda/d71/
Dd71_component.c90 static void dump_block_header(struct seq_file *sf, void __iomem *reg) in dump_block_header() argument
96 seq_printf(sf, "BLOCK_INFO:\t\t0x%X\n", hdr.block_info); in dump_block_header()
97 seq_printf(sf, "PIPELINE_INFO:\t\t0x%X\n", hdr.pipeline_info); in dump_block_header()
103 seq_printf(sf, "VALID_INPUT_ID%u:\t0x%X\n", in dump_block_header()
107 seq_printf(sf, "OUTPUT_ID%u:\t\t0x%X\n", in dump_block_header()
288 static void d71_layer_dump(struct komeda_component *c, struct seq_file *sf) in d71_layer_dump() argument
305 dump_block_header(sf, c->reg); in d71_layer_dump()
307 seq_printf(sf, "%sLAYER_INFO:\t\t0x%X\n", prefix, v[14]); in d71_layer_dump()
310 seq_printf(sf, "%sCONTROL:\t\t0x%X\n", prefix, v[0]); in d71_layer_dump()
313 seq_printf(sf, "LR_RICH_CONTROL:\t0x%X\n", v[0]); in d71_layer_dump()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_audio.h44 #define SF(reg_name, field_name, post_fix)\ macro
49 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
50 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
51 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
52 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
53 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
54 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
55 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
56 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
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