| /linux-6.12.1/arch/arm/mach-bcm/ |
| D | platsmp.c | 33 /* Name of device node property defining secondary boot register location */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
91 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
120 /* Ensure the write is visible to the secondary core */ in nsp_write_lut()
141 * The ROM code has the secondary cores looping, waiting for an event.
143 * secondary boot register. When a core finds those bits contain its
147 * address back to the secondary boot register, and finally jumps to
151 * - Encode the (hardware) CPU id with the bottom bits of the secondary
153 * - Write that value into the secondary boot register.
154 * - Generate an event to wake up the secondary CPU(s).
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| /linux-6.12.1/arch/sparc/include/uapi/asm/ |
| D | asi.h | 130 #define ASI_AIUS 0x11 /* Secondary, user */
132 #define ASI_AIUSL 0x19 /* Secondary, user, little endian */
134 #define ASI_S 0x81 /* Secondary, implicit */
136 #define ASI_SNF 0x83 /* Secondary, no fault */
138 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */
140 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
161 * secondary, user
231 #define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
242 #define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
255 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
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| /linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/lib/ |
| D | sd.c | 27 struct { /* secondary */
316 static int sd_secondary_create_alias_ft(struct mlx5_core_dev *secondary, in sd_secondary_create_alias_ft() argument
330 ret = mlx5_cmd_alias_obj_create(secondary, &alias_attr, obj_id); in sd_secondary_create_alias_ft()
332 mlx5_core_err(secondary, "Failed to create alias object err=%d\n", in sd_secondary_create_alias_ft()
340 static void sd_secondary_destroy_alias_ft(struct mlx5_core_dev *secondary) in sd_secondary_destroy_alias_ft() argument
342 struct mlx5_sd *sd = mlx5_get_sd(secondary); in sd_secondary_destroy_alias_ft()
344 mlx5_cmd_alias_obj_destroy(secondary, sd->alias_obj_id, in sd_secondary_destroy_alias_ft()
348 static int sd_cmd_set_secondary(struct mlx5_core_dev *secondary, in sd_cmd_set_secondary() argument
353 struct mlx5_sd *sd = mlx5_get_sd(secondary); in sd_cmd_set_secondary()
356 err = mlx5_fs_cmd_set_l2table_entry_silent(secondary, 1); in sd_cmd_set_secondary()
[all …]
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| /linux-6.12.1/certs/ |
| D | system_keyring.c | 77 * addition by both built-in and secondary keyrings.
84 * being vouched for by a key in either the built-in or the secondary system
93 /* If we have a secondary trusted keyring, then that contains a link in restrict_link_by_builtin_and_secondary_trusted()
99 /* Allow the builtin keyring to be added to the secondary */ in restrict_link_by_builtin_and_secondary_trusted()
114 * being vouched for by a key in either the built-in or the secondary system
122 /* If we have a secondary trusted keyring, then that contains a link in restrict_link_by_digsig_builtin_and_secondary()
128 /* Allow the builtin keyring to be added to the secondary */ in restrict_link_by_digsig_builtin_and_secondary()
136 * Allocate a struct key_restriction for the "builtin and secondary trust"
146 panic("Can't allocate secondary trusted keyring restriction\n"); in get_builtin_and_secondary_restriction()
157 * add_to_secondary_keyring - Add to secondary keyring.
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| /linux-6.12.1/sound/soc/qcom/qdsp6/ |
| D | q6dsp-lpass-ports.c | 360 .stream_name = "Secondary MI2S Playback",
373 .stream_name = "Secondary MI2S Capture",
483 Q6AFE_TDM_PB_DAI("Secondary", 0, SECONDARY_TDM_RX_0),
484 Q6AFE_TDM_PB_DAI("Secondary", 1, SECONDARY_TDM_RX_1),
485 Q6AFE_TDM_PB_DAI("Secondary", 2, SECONDARY_TDM_RX_2),
486 Q6AFE_TDM_PB_DAI("Secondary", 3, SECONDARY_TDM_RX_3),
487 Q6AFE_TDM_PB_DAI("Secondary", 4, SECONDARY_TDM_RX_4),
488 Q6AFE_TDM_PB_DAI("Secondary", 5, SECONDARY_TDM_RX_5),
489 Q6AFE_TDM_PB_DAI("Secondary", 6, SECONDARY_TDM_RX_6),
490 Q6AFE_TDM_PB_DAI("Secondary", 7, SECONDARY_TDM_RX_7),
[all …]
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| D | q6afe.h | 28 /* Clock ID for Secondary I2S IBIT */
30 /* Clock ID for Secondary I2S EBIT */
77 /* Clock ID for Secondary PCM IBIT */
79 /* Clock ID for Secondary PCM EBIT */
100 /** Clock ID for Secondary TDM IBIT */
102 /** Clock ID for Secondary TDM EBIT */
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| /linux-6.12.1/arch/arm64/include/asm/ |
| D | smp.h | 20 /* Fatal system error detected by secondary CPU, crash the system */
59 * Called from the secondary holding pen, this is the secondary CPU entry point.
64 * Initial data for bringing up a secondary CPU.
65 * @status - Result passed back from the secondary CPU to
111 * The calling secondary CPU has detected serious configuration mismatch,
122 * If a secondary CPU enters the kernel but fails to come online,
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| /linux-6.12.1/Documentation/admin-guide/blockdev/drbd/ |
| D | peer-states-8.dot | 2 Secondary -> Primary [ label = "recv state packet" ]
3 Primary -> Secondary [ label = "recv state packet" ]
5 Secondary -> Unknown [ label = "connection lost" ]
7 Unknown -> Secondary [ label = "connected" ]
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| /linux-6.12.1/Documentation/arch/sparc/oradax/ |
| D | dax-hv-api.txt | 172 [7:5] Secondary source address type
248 encoded data) and secondary data streams (meta-data for the encoded data).
260 … Variable width byte packed Data stream of lengths must be provided as a secondary
263 length encoding provided as a secondary input
267 as a secondary input
279 … a secondary input; pointer to the encoding table must be
291 … OZIP (CCB version 1) encoding as a secondary input; pointer to the encoding table must
296 … OZIP (CCB version 1) encoding stream of run lengths must be provided as a secondary
307 36.2.1.1.3. Secondary Input Format
309 …For primary input data streams which require a secondary input stream, the secondary input stream …
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | pamu.txt | 63 - fsl,secondary-cache-geometry
65 Two cells that specify the geometry of the secondary PAMU
108 fsl,secondary-cache-geometry = <128 2>;
114 fsl,secondary-cache-geometry = <128 2>;
120 fsl,secondary-cache-geometry = <128 2>;
126 fsl,secondary-cache-geometry = <128 2>;
132 fsl,secondary-cache-geometry = <128 2>;
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| /linux-6.12.1/arch/arm/mach-mvebu/ |
| D | headsmp.S | 3 * SMP support: Entry point for secondary CPUs
11 * This file implements the assembly entry point for secondary CPUs in
24 * Armada XP specific entry point for secondary CPUs.
25 * We add the CPU to the coherency fabric and then jump to secondary
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| /linux-6.12.1/arch/arm/mach-omap2/ |
| D | omap-headsmp.S | 3 * Secondary CPU startup routine source file.
21 /* Physical address needed since MMU not enabled yet on secondary core */
36 * OMAP5 specific entry point for secondary CPU to jump from ROM
38 * secondary core is held until we're ready for it to initialise.
75 * OMAP4 specific entry point for secondary CPU to jump from ROM
77 * secondary core is held until we're ready for it to initialise.
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| /linux-6.12.1/arch/arm/mach-versatile/ |
| D | platsmp.c | 45 * calibrations on the secondary CPU while the requesting CPU is using
72 * and the secondary one in versatile_boot_secondary()
77 * This is really belt and braces; we hold unintended secondary in versatile_boot_secondary()
85 * Send the secondary CPU a soft interrupt, thereby causing in versatile_boot_secondary()
101 * now the secondary core is starting up let it run its in versatile_boot_secondary()
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| /linux-6.12.1/Documentation/arch/arm/samsung/ |
| D | bootloader-interface.rst | 28 0x1c exynos4_secondary_startup Secondary CPU boot
29 0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
44 0x00 exynos4_secondary_startup Secondary CPU boot
45 0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
46 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
60 0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot
72 0x0908 Non-zero Secondary CPU boot up indicator
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| /linux-6.12.1/arch/arm/mach-spear/ |
| D | platsmp.c | 62 * and the secondary one in spear13xx_boot_secondary()
67 * The secondary processor is waiting to be released from in spear13xx_boot_secondary()
86 * now the secondary core is starting up let it run its in spear13xx_boot_secondary()
118 * Write the address of secondary startup into the system-wide location in spear13xx_smp_prepare_cpus()
120 * soft interrupt, and then the secondary CPU branches to this address. in spear13xx_smp_prepare_cpus()
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| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a-qds.dts | 110 mdio@0 { /* Slot #1 (secondary EMI) */
116 mdio@1 { /* Slot #2 (secondary EMI) */
122 mdio@2 { /* Slot #3 (secondary EMI) */
128 mdio@3 { /* Slot #4 (secondary EMI) */
134 mdio@4 { /* Slot #5 (secondary EMI) */
140 mdio@5 { /* Slot #6 (secondary EMI) */
146 mdio@6 { /* Slot #7 (secondary EMI) */
152 mdio@7 { /* Slot #8 (secondary EMI) */
|
| D | fsl-lx2162a-qds.dts | 120 mdio@0 { /* Slot #1 (secondary EMI) */
126 mdio@1 { /* Slot #2 (secondary EMI) */
132 mdio@2 { /* Slot #3 (secondary EMI) */
138 mdio@3 { /* Slot #4 (secondary EMI) */
144 mdio@4 { /* Slot #5 (secondary EMI) */
150 mdio@5 { /* Slot #6 (secondary EMI) */
156 mdio@6 { /* Slot #7 (secondary EMI) */
162 mdio@7 { /* Slot #8 (secondary EMI) */
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| /linux-6.12.1/arch/sparc/kernel/ |
| D | sbus.c | 264 #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
265 #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
266 #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
288 /* Clear primary/secondary error status bits. */ in sysio_ue_handler()
311 printk("SYSIO[%x]: Secondary UE errors [", portid); in sysio_ue_handler()
337 #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
338 #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
339 #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
362 /* Clear primary/secondary error status bits. */ in sysio_ce_handler()
390 printk("SYSIO[%x]: Secondary CE errors [", portid); in sysio_ce_handler()
[all …]
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| /linux-6.12.1/sound/arm/ |
| D | pxa2xx-ac97-regs.h | 28 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
30 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
58 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
60 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
96 #define SAC_REG_BASE (0x0300) /* Secondary Audio Codec */
98 #define SMC_REG_BASE (0x0500) /* Secondary Modem Codec */
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| /linux-6.12.1/Documentation/devicetree/bindings/sound/ |
| D | samsung-i2s.yaml | 22 secondary FIFO, s/w reset control and internal mux for root clock
26 playback, stereo channel capture, secondary FIFO using internal
33 Exynos7 I2S has 7.1 channel TDM support for capture, secondary FIFO
42 capture, secondary FIFO using external DMA, s/w reset control,
124 subsystem (used in secondary sound source).
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| /linux-6.12.1/arch/powerpc/platforms/powernv/ |
| D | subcore.h | 8 #define SYNC_STEP_UNSPLIT 1 /* Set by secondary when it sees unsplit */
9 #define SYNC_STEP_REAL_MODE 2 /* Set by secondary when in real mode */
10 #define SYNC_STEP_FINISHED 3 /* Set by secondary when split/unsplit is done */
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | uncore-interconnect.json | 111 … "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
116 …"PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
121 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
126 … "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
131 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
136 … "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
161 "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
166 … "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary",
171 "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
176 … "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary",
[all …]
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| /linux-6.12.1/include/linux/ |
| D | mmu_notifier.h | 70 * should tear down all secondary mmu mappings and freeze the
71 * secondary mmu. If this method isn't implemented you've to
73 * through the secondary mmu by the time the last thread with
80 * through the secondary mmu are terminated by the time the
95 * accesses to the page through the secondary MMUs and not
97 * Start-end is necessary in case the secondary MMU is mapping the page
108 * in the secondary pte, but it may omit flushing the secondary tlb.
117 * the secondary pte. This is used to know if the page is
119 * down the secondary mapping on the page.
163 * any secondary tlb before doing the final free on the
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/net/can/ |
| D | st,stm32-bxcan.yaml | 32 st,can-secondary:
34 Secondary mode of the bxCAN peripheral is only relevant if the chip
39 uses the terms slave instead of secondary.
70 secondary) in dual CAN peripheral configuration.
|
| /linux-6.12.1/drivers/net/wireless/intel/iwlwifi/mvm/ |
| D | coex.c | 214 struct ieee80211_chanctx_conf *secondary; member
253 swap(data->primary, data->secondary); in iwl_mvm_bt_coex_tcm_based_ci()
422 data->secondary = data->primary; in iwl_mvm_bt_notif_per_link()
438 data->secondary = data->primary; in iwl_mvm_bt_notif_per_link()
441 /* there is low latency vif - we will be secondary */ in iwl_mvm_bt_notif_per_link()
442 data->secondary = chanctx_conf; in iwl_mvm_bt_notif_per_link()
448 else if (data->secondary == chanctx_conf) in iwl_mvm_bt_notif_per_link()
459 else if (!data->secondary) in iwl_mvm_bt_notif_per_link()
460 /* if secondary is not NULL, it might be a GO */ in iwl_mvm_bt_notif_per_link()
461 data->secondary = chanctx_conf; in iwl_mvm_bt_notif_per_link()
[all …]
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