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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dhisilicon,hi3670-usb3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
17 const: hisilicon,hi3670-usb-phy
19 "#phy-cells":
22 hisilicon,pericrg-syscon:
24 description: phandle of syscon used to control iso refclk.
26 hisilicon,pctrl-syscon:
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/linux-6.12.1/drivers/phy/hisilicon/
Dphy-hi3670-usb3.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2017-2020 Hilisicon Electronics Co., Ltd.
14 #include <linux/mfd/syscon.h>
130 struct regmap *sctrl; member
190 while (retry-- > 0) { in hi3670_phy_cr_wait_ack()
204 return -ETIMEDOUT; in hi3670_phy_cr_wait_ack()
294 ret = regmap_write(priv->usb31misc, USB3OTG_CTRL4, in hi3670_phy_set_params()
295 priv->eye_diagram_param); in hi3670_phy_set_params()
297 dev_err(priv->dev, "set USB3OTG_CTRL4 failed\n"); in hi3670_phy_set_params()
301 while (retry-- > 0) { in hi3670_phy_set_params()
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Dphy-hi3670-pcie.c1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/mfd/syscon.h>
171 writel(val, phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_writel()
176 return readl(phy->base + APB_PHY_START_ADDR + reg); in hi3670_apb_phy_readl()
193 writel(val, phy->base + reg); in kirin_apb_natural_phy_writel()
199 return readl(phy->base + reg); in kirin_apb_natural_phy_readl()
206 regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val); in hi3670_pcie_phy_oe_enable()
212 regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val); in hi3670_pcie_phy_oe_enable()
217 struct device *dev = phy->dev; in hi3670_pcie_get_eyeparam()
221 np = dev->of_node; in hi3670_pcie_get_eyeparam()
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/linux-6.12.1/arch/arm64/boot/dts/hisilicon/
Dhi3670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
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Dhi3660.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
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Dhi6220.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dhi6220-clock.txt11 - compatible: the compatible should be one of the following strings to
14 - "hisilicon,hi6220-acpu-sctrl"
15 - "hisilicon,hi6220-aoctrl"
16 - "hisilicon,hi6220-sysctrl"
17 - "hisilicon,hi6220-mediactrl"
18 - "hisilicon,hi6220-pmctrl"
19 - "hisilicon,hi6220-stub-clk"
21 - reg: physical base address of the controller and length of memory mapped
24 - #clock-cells: should be 1.
28 - hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
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Dhi3670-clock.txt8 - compatible: the compatible should be one of the following strings to
11 - "hisilicon,hi3670-crgctrl"
12 - "hisilicon,hi3670-pctrl"
13 - "hisilicon,hi3670-pmuctrl"
14 - "hisilicon,hi3670-sctrl"
15 - "hisilicon,hi3670-iomcu"
16 - "hisilicon,hi3670-media1-crg"
17 - "hisilicon,hi3670-media2-crg"
19 - reg: physical base address of the controller and length of memory mapped
22 - #clock-cells: should be 1.
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Dhi3660-clock.txt8 - compatible: the compatible should be one of the following strings to
11 - "hisilicon,hi3660-crgctrl"
12 - "hisilicon,hi3660-pctrl"
13 - "hisilicon,hi3660-pmuctrl"
14 - "hisilicon,hi3660-sctrl"
15 - "hisilicon,hi3660-iomcu"
16 - "hisilicon,hi3660-stub-clk"
18 - reg: physical base address of the controller and length of memory mapped
21 - #clock-cells: should be 1.
25 - mboxes: Phandle to the mailbox for sending message to MCU.
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/linux-6.12.1/arch/arm64/boot/dts/bitmain/
Dbm1880.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
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/linux-6.12.1/drivers/pci/controller/dwc/
Dpcie-kirin.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon.h>
27 #include "pcie-designware.h"
29 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
58 * in-board Ethernet adapter and the other two connected to M.2 and mini
81 /* Per-slot PERST# */
86 /* Per-slot clkreq */
140 writel(val, hi3660_pcie_phy->base + reg); in kirin_apb_phy_writel()
146 return readl(hi3660_pcie_phy->base + reg); in kirin_apb_phy_readl()
151 struct device *dev = phy->dev; in hi3660_pcie_phy_get_clk()
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