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/linux-6.12.1/arch/riscv/include/asm/
Dcompat.h67 compat_ulong_t s11; member
104 cregs->s11 = (compat_ulong_t) regs->s11; in regs_to_cregs()
141 regs->s11 = (unsigned long) cregs->s11; in cregs_to_regs()
Dkgdb.h61 #define DBG_REG_S11 "s11"
Dassembler.h59 REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
/linux-6.12.1/drivers/media/rc/img-ir/
Dimg-ir-hw.h93 * @s11: One symbol timing data for secondary (no leader symbol) decoder
97 struct img_ir_symbol_timing ldr, s00, s01, s10, s11; member
121 * @s11: One symbol timing register value for secondary decoder
125 u32 ldr, s00, s01, s10, s11, ft; member
Dimg-ir-hw.c91 img_ir_symbol_timing_preprocess(&timings->s11, unit); in img_ir_timings_preprocess()
92 /* default s10 and s11 to s00 and s01 if no leader */ in img_ir_timings_preprocess()
123 img_ir_symbol_timing_defaults(&timings->s11, &defaults->s11); in img_ir_timings_defaults()
305 regs->s11 = img_ir_symbol_timing(&timings->s11, tolerance, clock_hz, in img_ir_timings_convert()
387 img_ir_write(priv, IMG_IR_S11_SYMB_TIMING, regs->s11); in img_ir_write_timings()
390 regs->ldr, regs->s00, regs->s01, regs->s10, regs->s11, ft); in img_ir_write_timings()
Dimg-ir-rc5.c68 .s11 = {
Dimg-ir-sharp.c88 .s11 = {
/linux-6.12.1/Documentation/devicetree/bindings/regulator/
Dqcom,smd-rpm-regulator.yaml61 For pm8994, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3,
65 For pm8998, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2,
69 For pma8084, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3,
/linux-6.12.1/drivers/regulator/
Dqcom-rpmh-regulator.c937 RPMH_VREG("smps11", "smp%s11", &pmic4_ftsmps426, "vdd-s11"),
950 RPMH_VREG("ldo11", "ldo%s11", &pmic4_nldo, "vdd-l3-l11"),
1012 RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l1-l8-l11"),
1042 RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l7-l11"),
1068 RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo, "vdd-l1-l8-l11"),
1112 RPMH_VREG("smps11", "smp%s11", &pmic5_hfsmps510, "vdd-s11"),
1148 RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l6-l9-l11"),
1180 RPMH_VREG("ldo11", "ldo%s11", &pmic5_nldo515, "vdd-l11"),
1287 RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo_lv, "vdd-l11-l12-l13"),
1318 RPMH_VREG("ldo11", "ldo%s11", &pmic5_pldo, "vdd-l7-l11"),
[all …]
/linux-6.12.1/arch/riscv/kvm/
Dvcpu_switch.S42 REG_S s11, (KVM_ARCH_HOST_S11)(a0)
102 REG_L s11, (KVM_ARCH_GUEST_S11)(a0)
146 REG_S s11, (KVM_ARCH_GUEST_S11)(a0)
207 REG_L s11, (KVM_ARCH_HOST_S11)(a0)
/linux-6.12.1/arch/riscv/kernel/
Dkexec_relocate.S124 mv s11, zero
188 mv s11, zero
Dprocess.c89 pr_cont(" s11: " REG_FMT " t3 : " REG_FMT " t4 : " REG_FMT "\n", in __show_regs()
90 regs->s11, regs->t3, regs->t4); in __show_regs()
Dcrash_save_regs.S40 REG_S s11, PT_S11(a0) /* x27 */
Dsuspend_entry.S43 REG_S s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
Dentry.S398 REG_S s11, TASK_THREAD_S11_RA(a3)
415 REG_L s11, TASK_THREAD_S11_RA(a4)
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dmsm8992-xiaomi-libra.dts185 /* APC1 is 3-phase, but quoting downstream, s11 is "the gang leader" */
186 VDD_APC1: s11 {
238 /* S8, S9, S10 and S11 - SPMI-managed VDD_APC */
/linux-6.12.1/arch/riscv/crypto/
Dchacha-riscv64-zvkb.S74 #define NONCE2 s11
155 sd s11, 88(sp)
291 ld s11, 88(sp)
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_sprite_regs.h358 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
360 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
376 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
378 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
/linux-6.12.1/tools/testing/selftests/kvm/lib/riscv/
Dprocessor.c252 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11), &core.regs.s11); in vcpu_arch_dump()
279 " S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n", in vcpu_arch_dump()
280 core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11); in vcpu_arch_dump()
/linux-6.12.1/tools/perf/util/perf-regs-arch/
Dperf_regs_riscv.c64 return "s11"; in __perf_reg_name_riscv()
/linux-6.12.1/tools/perf/arch/riscv/util/
Dunwind-libdw.c49 dwarf_regs[27] = REG(S11); in libdw__arch_set_initial_registers()
Ddwarf-regs.c48 REG_DWARFNUM_NAME("%s11", 27),
/linux-6.12.1/arch/arm/crypto/
Dblake2b-neon-core.S70 s8, s9, s10, s11, s12, s13, s14, s15, final=0
192 .if \s9 == 0 || \s11 == 0 || \s13 == 0 || \s15 == 0
200 vadd.u64 d1, d1, M_\s11
/linux-6.12.1/arch/riscv/include/uapi/asm/
Dptrace.h52 unsigned long s11; member
/linux-6.12.1/tools/testing/selftests/kvm/include/riscv/
Dprocessor.h90 unsigned long s11; member

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