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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Drenesas,rz-ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 - $ref: dai-common.yaml#
18 - enum:
19 - renesas,r9a07g043-ssi # RZ/G2UL and RZ/Five
20 - renesas,r9a07g044-ssi # RZ/G2{L,LC}
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Drenesas,rsnd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Sound Driver
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
17 - items:
18 - enum:
19 - renesas,rcar_sound-r8a7778 # R-Car M1A
20 - renesas,rcar_sound-r8a7779 # R-Car H1
21 - const: renesas,rcar_sound-gen1
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Drenesas,rsnd.txt1 Renesas R-Car sound
7 Renesas R-Car and RZ/G sound is constructed from below modules
11 - SRC : Sampling Rate Converter
12 - CMD
13 - CTU : Channel Transfer Unit
14 - MIX : Mixer
15 - DVC : Digital Volume and Mute Function
17 SSI : Serial Sound Interface
25 Multi channel is supported by Multi-SSI, or TDM-SSI.
27 Multi-SSI : 6ch case, you can use stereo x 3 SSI
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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/linux-6.12.1/sound/soc/sh/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 snd-soc-dma-sh7760-y := dma-sh7760.o
4 obj-$(CONFIG_SND_SOC_PCM_SH7760) += snd-soc-dma-sh7760.o
6 ## audio units found on some SH-4
7 snd-soc-hac-y := hac.o
8 snd-soc-ssi-y := ssi.o
9 snd-soc-fsi-y := fsi.o
10 snd-soc-siu-y := siu_pcm.o siu_dai.o
11 obj-$(CONFIG_SND_SOC_SH4_HAC) += snd-soc-hac.o
12 obj-$(CONFIG_SND_SOC_SH4_SSI) += snd-soc-ssi.o
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Drz-ssi.c1 // SPDX-License-Identifier: GPL-2.0
3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver
27 /* SSI REGISTER BITS */
74 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-44.1kHz */
85 int fifo_sample_size; /* sample capacity of SSI FIFO */
97 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm);
117 * The SSI supports full-duplex transmission and reception.
120 * So it is better to use as half-duplex (playing and recording
148 writel(data, (priv->base + reg)); in rz_ssi_reg_writel()
153 return readl(priv->base + reg); in rz_ssi_reg_readl()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
40 tristate "R-Car series SRU/SCU/SSIU/SSI support"
47 This option enables R-Car SRU/SCU/SSIU/SSI sound support
50 tristate "RZ/G2L series SSIF-2 support"
53 This option enables RZ/G2L SSIF-2 sound support.
69 tristate "SIU sound support on Migo-R"
74 This option enables sound support for the SH7722 Migo-R board
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
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Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
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Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/V2L SoC
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
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Dr9a07g044c2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2LC R9A07G044C2 SoC specific parts
8 /dts-v1/;
16 /delete-node/ ssi@1004a800;
17 /delete-node/ serial@1004c800;
18 /delete-node/ adc@10059000;
19 /delete-node/ ethernet@11c30000;
Dr9a07g044c1.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts
8 /dts-v1/;
15 /delete-node/ cpu-map;
16 /delete-node/ cpu@100;
21 /delete-node/ ssi@1004a800;
22 /delete-node/ serial@1004c800;
23 /delete-node/ adc@10059000;
24 /delete-node/ ethernet@11c30000;
Dhihope-rev4.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
4 * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
9 #include <dt-bindings/gpio/gpio.h>
10 #include "hihope-common.dtsi"
13 audio_clkout: audio-clkout {
16 * but needed to avoid cs2000/rcar_sound probe dead-lock
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <12288000>;
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Drz-smarc-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 * SSI-WM8978
32 stdout-path = "serial0:115200n8";
36 compatible = "simple-audio-card";
37 simple-audio-card,format = "i2s";
38 simple-audio-card,bitclock-master = <&cpu_dai>;
39 simple-audio-card,frame-master = <&cpu_dai>;
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Dr8a774c0-cat874.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/display/tda998x.h>
14 model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
15 compatible = "si-linux,cat874", "renesas,r8a774c0";
26 stdout-path = "serial0:115200n8";
29 hdmi-out {
30 compatible = "hdmi-connector";
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Dr8a774c0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
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/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr8a7742-iwg21d-q7.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZ/G1H Qseven board
9 * SSI-SGTL5000
31 /dts-v1/;
32 #include "r8a7742-iwg21m.dtsi"
33 #include <dt-bindings/pwm/pwm.h>
36 model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H";
47 stdout-path = "serial2:115200n8";
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
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Dr8a7745-iwg22d-sodimm.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZG1E SODIMM carrier board
9 * SSI-SGTL5000
31 /dts-v1/;
32 #include "r8a7745-iwg22m.dtsi"
33 #include <dt-bindings/pwm/pwm.h>
36 model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E";
47 stdout-path = "serial3:115200n8";
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
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Diwg20d-q7-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
9 * SSI-SGTL5000
40 stdout-path = "serial0:115200n8";
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <26000000>;
50 compatible = "pwm-backlight";
53 brightness-levels = <0 4 8 16 32 64 128 255>;
54 default-brightness-level = <7>;
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/linux-6.12.1/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
23 (half duplex), SSP, SSI, and PSP. This driver framework should
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
155 supports spi-mem interface.
234 this code to manage the per-word or per-transfer accesses to the
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/linux-6.12.1/drivers/clk/renesas/
Dr8a7743-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/soc/renesas/rcar-rst.h>
14 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
16 #include "renesas-cpg-mssr.h"
17 #include "rcar-gen2-cpg.h"
86 DEF_MOD("2d-dmac", 115, R8A7743_CLK_ZS),
87 DEF_MOD("fdp1-1", 118, R8A7743_CLK_ZS),
88 DEF_MOD("fdp1-0", 119, R8A7743_CLK_ZS),
104 DEF_MOD("sys-dmac1", 218, R8A7743_CLK_ZS),
105 DEF_MOD("sys-dmac0", 219, R8A7743_CLK_ZS),
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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