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Searched +full:rx +full:- +full:common +full:- +full:refclk +full:- +full:mode (Results 1 – 25 of 30) sorted by relevance

12

/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-snps-pcie3.c1 // SPDX-License-Identifier: GPL-2.0
57 /* mode: RC, EP */
58 int mode; member
76 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) in rockchip_p3phy_set_mode() argument
80 /* Actually We don't care EP/RC mode, but just record it */ in rockchip_p3phy_set_mode()
83 priv->mode = PHY_MODE_PCIE_RC; in rockchip_p3phy_set_mode()
86 priv->mode = PHY_MODE_PCIE_EP; in rockchip_p3phy_set_mode()
89 dev_err(&phy->dev, "%s, invalid mode\n", __func__); in rockchip_p3phy_set_mode()
90 return -EINVAL; in rockchip_p3phy_set_mode()
98 struct phy *phy = priv->phy; in rockchip_p3phy_rk3568_init()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3588-rock-5b-pcie-srns.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex
4 * mode in the SRNS (Separate Reference Clock No Spread) configuration.
7 * a setup with two ROCK 5B:s, with one board running in RC mode and the
8 * other board running in EP mode.
11 /dts-v1/;
15 rockchip,rx-common-refclk-mode = <0 0 0 0>;
Drk3588-rock-5b-pcie-ep.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode
7 * RC mode and the other board running in EP mode, see also the device
8 * tree overlay: rk3588-rock-5b-pcie-srns.dtso.
11 /dts-v1/;
15 rockchip,rx-common-refclk-mode = <0 0 0 0>;
23 vpcie3v3-supply = <&vcc3v3_pcie30>;
Drk3568-qnap-ts433.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (c) 2024 Uwe Kleine-König
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/gpio/gpio.h>
15 model = "Qnap TS-433-4G NAS System 4-Bay";
25 stdout-path = "serial2:115200n8";
29 compatible = "gpio-keys";
30 pinctrl-0 = <&copy_button_pin>, <&reset_button_pin>;
[all …]
Drk3588-rock-5-itx.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/pwm/pwm.h>
14 #include "dt-bindings/usb/pd.h"
19 compatible = "radxa,rock-5-itx", "rockchip,rk3588";
28 stdout-path = "serial2:1500000n8";
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Drockchip,pcie3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-pcie3-phy
16 - rockchip,rk3588-pcie3-phy
25 clock-names:
29 data-lanes:
32 (controller-number +1 )
[all …]
/linux-6.12.1/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
58 /* PLL Test Mode register parameters */
105 /* Refclk selection parameters */
136 /* Test Mode common reset control parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
198 * struct xpsgtr_phy - representation of a lane
[all …]
/linux-6.12.1/drivers/media/i2c/
Dds90ub960.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Texas Instruments DS90UB960-Q1 video deserializer
12 * - PM for serializer and remote peripherals. We need to manage:
13 * - VPOC
14 * - Power domain? Regulator? Somehow any remote device should be able to
16 * - Link between the deserializer and the serializer
17 * - Related to VPOC management. We probably always want to turn on the VPOC
19 * - Serializer's services: i2c, gpios, power
20 * - The serializer needs to resume before the remote peripherals can
22 * - How to handle gpios? Reserving a gpio essentially keeps the provider
[all …]
/linux-6.12.1/arch/riscv/boot/dts/microchip/
Dmpfs-icicle-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
7 #include "mpfs-icicle-kit-fabric.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
12 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
26 stdout-path = "serial1:115200n8";
30 compatible = "gpio-leds";
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/usb/
Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
35 - const: snps,dwc3
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6q-bosch-acc.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Support for the i.MX6-based Bosch ACC board.
8 * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
20 compatible = "bosch,imx6q-acc", "fsl,imx6q";
37 backlight_lvds: backlight-lvds {
38 compatible = "pwm-backlight";
40 brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
[all …]
/linux-6.12.1/drivers/phy/marvell/
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
228 enum phy_mode mode; member
235 .mode = _mode, \
274 enum phy_mode mode; member
285 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
298 /* 40M1G25 mode init data */
[all …]
Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
108 /* Relative to priv->regmap */
130 * [ 1- 0]: COMPHY polarity invertion
131 * [ 2- 7]: COMPHY speed
132 * [ 5-11]: COMPHY port index
133 * [12-16]: COMPHY mode
135 * [18-20]: PCIe width (x1, x2, x4)
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mp-venice-gw74xx.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/net/ti-dp83867.h>
18 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
31 stdout-path = &uart2;
40 pinctrl-names = "default";
[all …]
Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
27 stdout-path = &uart2;
36 compatible = "fixed-clock";
[all …]
Dimx8mm-venice-gw7903.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
25 stdout-path = &uart2;
33 gpio-keys {
34 compatible = "gpio-keys";
[all …]
Dimx8mp-tqma8mpql-mba8mp-ras314.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2023-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 #include <dt-bindings/pwm/pwm.h>
15 #include "imx8mp-tqma8mpql.dtsi"
18 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";
[all …]
Dimx8mp-tqma8mpql-mba8mpxl.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-group.com>
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "imx8mp-tqma8mpql.dtsi"
16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
[all …]
/linux-6.12.1/drivers/net/wireless/st/cw1200/
Dmain.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mac80211 glue code for mac80211 ST-Ericsson CW1200 drivers
5 * Copyright (c) 2010, ST-Ericsson
10 * Copyright (c) 2007-2009, Christian Lamparter <chunkeey@web.de>
14 * - the islsm (softmac prism54) driver, which is:
15 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
16 * - stlc45xx driver
17 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
40 MODULE_DESCRIPTION("Softmac ST-Ericsson CW1200 common code");
58 MODULE_PARM_DESC(cw1200_power_mode, "WSM power mode. 0 == active, 1 == doze, 2 == quiescent (defau…
[all …]
/linux-6.12.1/drivers/phy/cadence/
Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
189 /* PMA RX Lane registers */
221 /* PHY PCS common registers */
231 /* PHY PMA common registers */
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
[all …]
/linux-6.12.1/sound/soc/codecs/
Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // Cirrus Logic Madera class codecs common support
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
18 #include <linux/irqchip/irq-madera.h>
22 #include <sound/madera-pdata.h>
24 #include <dt-bindings/sound/madera.h>
143 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
145 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
147 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
150 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
[all …]
/linux-6.12.1/drivers/net/ethernet/cadence/
Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
33 #define MACB_RBQP 0x0018 /* RX Q Base Address */
86 #define GEM_PBUFRXCUT 0x0044 /* RX Partial Store and Forward */
100 #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
116 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
117 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
118 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Cheza device tree source (common between revisions)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power-supply = <&ppvar_sys>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&ap_edp_bklten>;
[all …]

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