Searched +full:reset +full:- +full:post +full:- +full:delay +full:- +full:us (Results 1 – 25 of 243) sorted by relevance
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/linux-6.12.1/Documentation/devicetree/bindings/net/ |
D | mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 17 bus. These should follow the generic ethernet-phy.yaml document, or 22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$' 24 "#address-cells": 27 "#size-cells": [all …]
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D | hisilicon-femac.txt | 4 - compatible: should contain one of the following version strings: 5 * "hisilicon,hisi-femac-v1" 6 * "hisilicon,hisi-femac-v2" 7 and the soc string "hisilicon,hi3516cv300-femac". 8 - reg: specifies base physical address(s) and size of the device registers. 11 - interrupts: should contain the MAC interrupt. 12 - clocks: A phandle to the MAC main clock. 13 - resets: should contain the phandle to the MAC reset signal(required) and 14 the PHY reset signal(optional). 15 - reset-names: should contain the reset signal name "mac"(required) [all …]
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D | hisilicon-hix5hd2-gmac.txt | 4 - compatible: should contain one of the following SoC strings: 5 * "hisilicon,hix5hd2-gmac" 6 * "hisilicon,hi3798cv200-gmac" 7 * "hisilicon,hi3516a-gmac" 9 * "hisilicon,hisi-gmac-v1" 10 * "hisilicon,hisi-gmac-v2" 13 - reg: specifies base physical address(s) and size of the device registers. 16 - interrupts: should contain the MAC interrupt. 17 - #address-cells: must be <1>. 18 - #size-cells: must be <0>. [all …]
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D | renesas,ethertsn.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas Ethernet TSN End-station 10 - Niklas Söderlund <niklas.soderlund@ragnatech.se> 14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY. 17 - $ref: ethernet-controller.yaml# 22 - enum: 23 - renesas,r8a779g0-ethertsn # R-Car V4H 24 - const: renesas,rcar-gen4-ethertsn [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/mmc/ |
D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ulf Hansson <ulf.hansson@linaro.org> 14 of common properties between various SOC designs. It thus enables us to use 19 const: mmc-pwrseq-simple 21 reset-gpios: 26 contains a list of GPIO specifiers. The reset GPIOs are asserted 28 They will be de-asserted right after the power has been provided to the [all …]
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/linux-6.12.1/arch/arm64/boot/dts/renesas/ |
D | white-hawk-ethernet.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 * Device Tree Source for the White Hawk RAVB/Ethernet(1000Base-T1) 4 * sub-board 17 pinctrl-0 = <&avb1_pins>; 18 pinctrl-names = "default"; 19 phy-handle = <&avb1_phy>; 23 #address-cells = <1>; 24 #size-cells = <0>; 26 reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; 27 reset-post-delay-us = <4000>; [all …]
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D | r8a779g2-white-hawk-single.dts | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 * Device Tree Source for the R-Car V4H ES2.0 White Hawk Single board 8 /dts-v1/; 10 #include "white-hawk-cpu-common.dtsi" 11 #include "white-hawk-common.dtsi" 15 compatible = "renesas,white-hawk-single", "renesas,r8a779g2", 20 uart-has-rtscts; 38 bias-disable; 43 drive-strength = <24>; 44 bias-disable; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/qcom/ |
D | sc7280-crd-r3.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 8 /dts-v1/; 10 #include "sc7280-idp.dtsi" 11 #include "sc7280-idp-ec-h1.dtsi" 14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)"; 15 compatible = "qcom,sc7280-crd", 16 "google,hoglin-rev3", "google,hoglin-rev4", 17 "google,piglin-rev3", "google,piglin-rev4", 25 stdout-path = "serial0:115200n8"; 30 regulators-2 { [all …]
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/linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
D | mt7986a-acelink-ew-7886cax.dts | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 /dts-v1/; 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/leds/common.h> 11 compatible = "acelink,ew-7886cax", "mediatek,mt7986a"; 12 model = "Acelink EW-7886CAX"; 19 stdout-path = "serial0:115200n8"; 28 compatible = "gpio-keys"; 30 key-restart { [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | imx93-var-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 12 model = "Variscite VAR-SOM-MX93 module"; 13 compatible = "variscite,var-som-mx93", "fsl,imx93"; 15 mmc_pwrseq: mmc-pwrseq { 16 compatible = "mmc-pwrseq-simple"; 17 post-power-on-delay-ms = <100>; 18 power-off-delay-us = <10000>; 19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ 23 reg_eqos_phy: regulator-eqos-phy { [all …]
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/linux-6.12.1/drivers/net/ethernet/emulex/benet/ |
D | be_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright (C) 2005-2016 Broadcom. 7 * linux-drivers@emulex.com 16 * The software must write this register twice to post any command. First, 33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */ 39 /* Soft Reset register masks */ 42 /* MPU semphore POST stage values */ 44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */ 45 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */ 46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ [all …]
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/linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
D | px30-engicam-common.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 15 vcc5v0_sys: vcc5v0-sys { 16 compatible = "regulator-fixed"; 17 regulator-name = "vcc5v0_sys"; /* +5V */ 18 regulator-always-on; 19 regulator-boot-on; 20 regulator-min-microvolt = <5000000>; 21 regulator-max-microvolt = <5000000>; 24 sdio_pwrseq: sdio-pwrseq { 25 compatible = "mmc-pwrseq-simple"; [all …]
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D | rk3566-radxa-zero-3w.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 5 #include "rk3566-radxa-zero-3.dtsi" 9 compatible = "radxa,zero-3w", "rockchip,rk3566"; 17 sdio_pwrseq: sdio-pwrseq { 18 compatible = "mmc-pwrseq-simple"; 20 clock-names = "ext_clock"; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&wifi_reg_on_h>; 23 post-power-on-delay-ms = <100>; [all …]
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/linux-6.12.1/arch/arm/boot/dts/nxp/imx/ |
D | imx6qdl-apf6.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/interrupt-controller/irq.h> 9 reg_1p8v: regulator-1p8v { 10 compatible = "regulator-fixed"; 11 regulator-name = "1P8V"; 12 regulator-min-microvolt = <1800000>; 13 regulator-max-microvolt = <1800000>; 14 regulator-always-on; 15 vin-supply = <®_3p3v>; [all …]
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D | mba6ulx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 3 * Copyright 2018-2022 TQ-Systems GmbH 4 * Author: Markus Niebel <Markus.Niebel@tq-group.com> 8 model = "TQ-Systems MBA6ULx Baseboard"; 18 stdout-path = &uart1; 22 compatible = "pwm-backlight"; 23 power-supply = <®_mba6ul_3v3>; 24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; 29 compatible = "gpio-beeper"; 33 gpio_buttons: gpio-keys { [all …]
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D | imx7d-flex-concentrator.dts | 1 // SPDX-License-Identifier: GPL-2.0 9 /dts-v1/; 11 #include "imx7d-tqma7.dtsi" 14 /delete-node/ &ds1339; 18 compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d"; 22 /* 1024 MB - TQMa7D board configuration */ 26 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 27 compatible = "regulator-fixed"; 28 regulator-name = "VBUS_USBOTG2"; 29 regulator-min-microvolt = <5000000>; [all …]
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/linux-6.12.1/arch/arm/boot/dts/st/ |
D | stm32mp15xx-dhcor-testbench.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 17 stdout-path = "serial0:115200n8"; 20 sd_switch: regulator-sd_switch { 21 compatible = "regulator-gpio"; 22 regulator-name = "sd_switch"; 23 regulator-min-microvolt = <1800000>; 24 regulator-max-microvolt = <2900000>; 25 regulator-type = "voltage"; 26 regulator-always-on; 29 gpios-states = <0>; [all …]
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/linux-6.12.1/drivers/w1/ |
D | w1_io.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 8 #include <linux/delay.h> 48 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level. 50 * @bit: 0 - write a 0, 1 - write a 0 read the level 54 if (dev->bus_master->touch_bit) in w1_touch_bit() 55 return dev->bus_master->touch_bit(dev->bus_master->data, bit); in w1_touch_bit() 66 * w1_write_bit() - Generates a write-0 or write-1 cycle. 70 * Only call if dev->bus_master->touch_bit is NULL 79 dev->bus_master->write_bit(dev->bus_master->data, 0); in w1_write_bit() 81 dev->bus_master->write_bit(dev->bus_master->data, 1); in w1_write_bit() [all …]
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/linux-6.12.1/arch/arm/boot/dts/actions/ |
D | owl-s500-roseapplepi.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Copyright (C) 2020-2021 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> 8 /dts-v1/; 10 #include "owl-s500.dtsi" 22 stdout-path = "serial2:115200n8"; 30 syspwr: regulator-5v0 { 31 compatible = "regulator-fixed"; 32 regulator-name = "SYSPWR"; 33 regulator-min-microvolt = <5000000>; 34 regulator-max-microvolt = <5000000>; [all …]
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/linux-6.12.1/drivers/mmc/core/ |
D | pwrseq_simple.c | 1 // SPDX-License-Identifier: GPL-2.0-only 18 #include <linux/delay.h> 39 struct gpio_descs *reset_gpios = pwrseq->reset_gpios; in mmc_pwrseq_simple_set_gpios_value() 43 int nvalues = reset_gpios->ndescs; in mmc_pwrseq_simple_set_gpios_value() 54 gpiod_set_array_value_cansleep(nvalues, reset_gpios->desc, in mmc_pwrseq_simple_set_gpios_value() 55 reset_gpios->info, values); in mmc_pwrseq_simple_set_gpios_value() 63 struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq); in mmc_pwrseq_simple_pre_power_on() 65 if (!IS_ERR(pwrseq->ext_clk) && !pwrseq->clk_enabled) { in mmc_pwrseq_simple_pre_power_on() 66 clk_prepare_enable(pwrseq->ext_clk); in mmc_pwrseq_simple_pre_power_on() 67 pwrseq->clk_enabled = true; in mmc_pwrseq_simple_pre_power_on() [all …]
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/linux-6.12.1/arch/arm64/boot/dts/allwinner/ |
D | sun50i-h5-nanopi-r1s-h5.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: 10 /dts-v1/; 11 #include "sun50i-h5.dtsi" 12 #include "sun50i-h5-cpu-opp.dtsi" 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/input/input.h> 16 #include <dt-bindings/leds/common.h> 20 compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; 29 stdout-path = "serial0:115200n8"; [all …]
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D | sun50i-h5-nanopi-neo-plus2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 /dts-v1/; 6 #include "sun50i-h5.dtsi" 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/pinctrl/sun4i-a10.h> 14 compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5"; 22 stdout-path = "serial0:115200n8"; 26 compatible = "gpio-leds"; 28 led-0 { [all …]
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/linux-6.12.1/arch/arm64/boot/dts/ti/ |
D | k3-j7200-evm-quad-port-eth-exp.dtso | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with 6 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 9 /dts-v1/; 12 #include <dt-bindings/gpio/gpio.h> 14 #include "k3-pinctrl.h" 15 #include "k3-serdes.h" 19 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 20 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 21 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; [all …]
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/linux-6.12.1/arch/arm/mach-omap2/ |
D | sram243x.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * linux/arch/arm/mach-omap2/sram243x.S 9 * Richard Woodruff <r-woodruff2@ti.com> 31 stmfd sp!, {r0 - r12, lr} @ save registers on stack 39 str r3, [r2] @ go to L1-freq operation 62 mov r9, #0x0 @ shift back to L0-voltage 67 str r3, [r2] @ go to L0-freq operation 69 /* reset entry mode for dllctrl */ 82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks [all …]
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D | sram242x.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * linux/arch/arm/mach-omap2/sram242x.S 9 * Richard Woodruff <r-woodruff2@ti.com> 31 stmfd sp!, {r0 - r12, lr} @ save registers on stack 39 str r3, [r2] @ go to L1-freq operation 62 mov r9, #0x0 @ shift back to L0-voltage 67 str r3, [r2] @ go to L0-freq operation 69 /* reset entry mode for dllctrl */ 82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks [all …]
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