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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24 "#address-cells":
27 "#size-cells":
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Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
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Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/power/reset/
Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
15 This binding supports level and edge triggered reset. At driver load time, the driver will
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
21 is configured as an output, and driven active, triggering a level triggered reset condition.
22 This will also cause an inactive->active edge condition, triggering positive edge triggered
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/panel/
Dsamsung,s6e8aa0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
22 reset-gpios: true
23 display-timings: true
25 vdd3-supply:
28 vci-supply:
31 power-on-delay:
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Dsamsung,ld9040.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 display-timings: true
25 reset-gpios: true
27 vdd3-supply:
30 vci-supply:
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/linux-6.12.1/include/linux/reset/
Dreset-simple.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Simple Reset Controller ops
5 * Based on Allwinner SoCs Reset Controller driver
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
16 #include <linux/reset-controller.h>
20 * struct reset_simple_data - driver data for simple reset controllers
21 * @lock: spinlock to protect registers during read-modify-write cycles
23 * @rcdev: reset controller device base structure
24 * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
25 * are set to assert the reset. Note that this says nothing about
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/linux-6.12.1/Documentation/devicetree/bindings/input/
Dnvidia,tegra20-kbc.txt7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
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/linux-6.12.1/drivers/scsi/qla4xxx/
Dql4_83xx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2013 QLogic Corporation
17 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()
22 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base()
31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base()
91 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock()
98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock()
169 flash_offset = addr & (QLA83XX_FLASH_SECTOR_SIZE - 1); in qla4_83xx_lockless_flash_read_u32()
188 (QLA83XX_FLASH_SECTOR_SIZE - 1)) { in qla4_83xx_lockless_flash_read_u32()
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/linux-6.12.1/include/linux/dma/
Dxilinx_dma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 #include <linux/dma-mapping.h>
15 * struct xilinx_vdma_config - VDMA Configuration structure
16 * @frm_dly: Frame delay
17 * @gen_lock: Whether in gen-lock mode
23 * @delay: Delay counter
24 * @reset: Reset Channel
36 int delay; member
37 int reset; member
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
19 - nvidia,tegra124-usb-phy
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/linux-6.12.1/drivers/video/backlight/
Dlms283gf05.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * lms283gf05.c -- support for Samsung LMS283GF05 LCD
10 #include <linux/delay.h>
21 struct gpio_desc *reset; member
27 unsigned char delay; member
32 /* REG, VALUE, DELAY */
95 gpiod_set_value(gpiod, 0); /* De-asserted */ in lms283gf05_reset()
99 gpiod_set_value(gpiod, 0); /* De-asserted */ in lms283gf05_reset()
120 mdelay(seq[i].delay); in lms283gf05_toggle()
127 struct spi_device *spi = st->spi; in lms283gf05_power_set()
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/linux-6.12.1/drivers/iio/imu/
Dadis.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/delay.h>
27 * __adis_write_reg() - write N bytes to register (unlocked version)
41 .tx_buf = adis->tx, in __adis_write_reg()
45 .delay.value = adis->data->write_delay, in __adis_write_reg()
46 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
48 .tx_buf = adis->tx + 2, in __adis_write_reg()
52 .delay.value = adis->data->write_delay, in __adis_write_reg()
53 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
[all …]
/linux-6.12.1/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_83xx_init.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
11 /* Reset template definitions */
74 u16 delay; member
78 u16 delay;
125 "Need Reset",
136 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE); in qlcnic_83xx_idc_check_driver_presence_reg()
146 cur = adapter->ahw->idc.curr_state; in qlcnic_83xx_idc_log_state_history()
147 prev = adapter->ahw->idc.prev_state; in qlcnic_83xx_idc_log_state_history()
149 dev_info(&adapter->pdev->dev, in qlcnic_83xx_idc_log_state_history()
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/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/
Dvitesse,vsc73xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
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/linux-6.12.1/drivers/input/misc/
Dpmic8xxx-pwrkey.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
32 /* Regulator control registers for shutdown/reset */
52 /* Buck TEST2 registers for shutdown/reset */
71 * struct pmic8xxx_pwrkey - pmic8xxx pwrkey information
107 enable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_suspend()
117 disable_irq_wake(pwrkey->key_press_irq); in pmic8xxx_pwrkey_resume()
130 bool reset = system_state == SYSTEM_RESTART; in pmic8xxx_pwrkey_shutdown() local
132 if (pwrkey->shutdown_fn) { in pmic8xxx_pwrkey_shutdown()
133 error = pwrkey->shutdown_fn(pwrkey, reset); in pmic8xxx_pwrkey_shutdown()
[all …]
/linux-6.12.1/drivers/mmc/host/
Dsdhci-of-dwcmshc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/arm-smccc.h>
14 #include <linux/dma-mapping.h>
21 #include <linux/reset.h>
24 #include "sdhci-pltfm.h"
41 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
51 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
53 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
118 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */
139 /* PHY reset pad settings */
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Dsdhci-bcm-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/delay.h>
14 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
52 /* This timeout should be sufficent for core to reset */ in sdhci_bcm_kona_sd_reset()
55 /* reset the host using the top level reset */ in sdhci_bcm_kona_sd_reset()
62 pr_err("Error: sd host is stuck in reset!!!\n"); in sdhci_bcm_kona_sd_reset()
63 return -EFAULT; in sdhci_bcm_kona_sd_reset()
67 /* bring the host out of reset */ in sdhci_bcm_kona_sd_reset()
72 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
[all …]
/linux-6.12.1/include/linux/usb/
Disp1362.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * board initialization code should put one of these into dev->platform_data
15 /* On-chip overcurrent protection */
33 /* Hardware reset set/clear */
34 void (*reset) (struct device *dev, int set); member
37 /* Inter-io delay (ns). The chip is picky about access timings; it
39 * 110ns delay between consecutive accesses to DATA_REG,
40 * 300ns delay between access to ADDR_REG and DATA_REG (registers)
41 * 462ns delay between access to ADDR_REG and DATA_REG (buffer memory)
44 void (*delay) (struct device *dev, unsigned int delay); member
/linux-6.12.1/Documentation/devicetree/bindings/reset/
Dnxp,lpc1850-rgu.txt1 NXP LPC1850 Reset Generation Unit (RGU)
4 Please also refer to reset.txt in this directory for common reset
8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
14 See table below for valid peripheral reset numbers. Numbers not
18 Reset Peripheral
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
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/linux-6.12.1/drivers/phy/qualcomm/
Dphy-qcom-m31.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014-2023, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
15 #include <linux/reset.h>
76 u32 delay; member
93 .delay = 15
200 struct reset_control *reset; member
208 const struct m31_phy_regs *regs = qphy->regs; in m31usb_phy_init()
211 ret = regulator_enable(qphy->vreg); in m31usb_phy_init()
213 dev_err(&phy->dev, "failed to enable regulator, %d\n", ret); in m31usb_phy_init()
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
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/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3588-turing-rk1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Based on RK3588-EVB1 devicetree
11 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
24 fan: pwm-fan {
25 compatible = "pwm-fan";
26 cooling-levels = <0 25 95 145 195 255>;
27 fan-supply = <&vcc5v0_sys>;
28 pinctrl-names = "default";
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