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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
27 - const: snps,dw-pcie
[all …]
/linux-6.12.1/lib/zstd/compress/
Dzstd_compress.c5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
11 /*-*************************************
43 * Maximum size of the hash table dedicated to find 3-bytes matches,
54 /*-*************************************
59 * full-block strategy.
69 /*-*************************************
84 … * row-based matchfinder. Unless the cdict is reloaded, we will use
96 assert(cctx != NULL); in ZSTD_initCCtx()
98 cctx->customMem = memManager; in ZSTD_initCCtx()
[all …]
Dzstd_compress_internal.h5 * This source code is licensed under both the BSD-style license (found in the
8 * You may select, at your option, one of the above-listed licenses.
18 /*-*************************************
25 /*-*************************************
35 … benefit is that ZSTD_DUBT_UNSORTED_MARK cannot be mishandled after table re-use with a different …
39 /*-*************************************
82 * Stores Literals Block Type for a super-block in hType, and
93 * Stores symbol compression modes for a super-block in {ll, ol, ml}Type, and
158 /* All tables are allocated inside cctx->workspace by ZSTD_resetCCtx_internal() */
174 …ZSTD_OptPrice_e priceType; /* prices can be determined dynamically, or follow a pre-defined cost…
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/linux-6.12.1/Documentation/devicetree/bindings/rtc/
Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
14 - if:
20 - ingenic,jz4770-rtc
21 - ingenic,jz4780-rtc
24 "#clock-cells": false
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/linux-6.12.1/drivers/pci/controller/
Dpcie-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
22 #include <linux/reset.h>
25 #include "pcie-rockchip.h"
29 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
31 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
35 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
38 "axi-base"); in rockchip_pcie_parse_dt()
39 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); in rockchip_pcie_parse_dt()
[all …]
/linux-6.12.1/drivers/scsi/
Dmesh.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
12 * Add delay after initial bus reset
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
[all …]
Dmesh.h1 /* SPDX-License-Identifier: GPL-2.0 */
64 #define SEQ_ATN 0x20 /* assert ATN signal */
80 #define SEQ_RESETMESH 0x0e /* reset the controller */
114 #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */
135 * The units of the sel_timeout register are 10ms.
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
11 chip's !RESET pin. If specified, the driver will
12 assert a hardware reset at probe time.
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
20 When not specified, the hardware default of 1300ms
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/linux-6.12.1/drivers/gpu/drm/panel/
Dpanel-samsung-s6d27a1.c1 // SPDX-License-Identifier: GPL-2.0
4 * Found in the Samsung Galaxy Ace 2 GT-I8160 mobile phone.
15 #include <linux/media-bus-format.h>
46 struct gpio_desc *reset; member
76 struct mipi_dbi *dbi = &ctx->dbi; in s6d27a1_read_mtp_id()
82 dev_err(ctx->dev, "unable to read MTP ID 1\n"); in s6d27a1_read_mtp_id()
87 dev_err(ctx->dev, "unable to read MTP ID 2\n"); in s6d27a1_read_mtp_id()
92 dev_err(ctx->dev, "unable to read MTP ID 3\n"); in s6d27a1_read_mtp_id()
95 dev_info(ctx->dev, "MTP ID: %02x %02x %02x\n", id1, id2, id3); in s6d27a1_read_mtp_id()
100 struct mipi_dbi *dbi = &ctx->dbi; in s6d27a1_power_on()
[all …]
Dpanel-samsung-db7430.c1 // SPDX-License-Identifier: GPL-2.0
5 * Found in the Samsung Galaxy Beam GT-I8350 mobile phone.
16 #include <linux/media-bus-format.h>
49 * struct db7430 - state container for a panel controlled by the DB7430
59 /** @reset: reset GPIO line */
60 struct gpio_desc *reset; member
91 struct mipi_dbi *dbi = &db->dbi; in db7430_power_on()
95 ret = regulator_bulk_enable(ARRAY_SIZE(db->regulators), in db7430_power_on()
96 db->regulators); in db7430_power_on()
98 dev_err(db->dev, "failed to enable regulators: %d\n", ret); in db7430_power_on()
[all …]
Dpanel-widechips-ws2401.c1 // SPDX-License-Identifier: GPL-2.0
5 * Found in the Samsung Galaxy Ace 2 GT-I8160 mobile phone.
7 * Inspired by code and know-how in the vendor driver by Gareth Phillips.
18 #include <linux/media-bus-format.h>
58 * struct ws2401 - state container for a panel controlled by the WS2401
72 /** @reset: reset GPIO line */
73 struct gpio_desc *reset; member
106 struct mipi_dbi *dbi = &ws->dbi; in ws2401_read_mtp_id()
112 dev_err(ws->dev, "unable to read MTP ID 1\n"); in ws2401_read_mtp_id()
117 dev_err(ws->dev, "unable to read MTP ID 2\n"); in ws2401_read_mtp_id()
[all …]
/linux-6.12.1/drivers/rtc/
Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
97 return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, in jz4780_rtc_enable_write()
106 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
111 writel(val, rtc->base + reg); in jz4740_rtc_reg_write()
123 spin_lock_irqsave(&rtc->lock, flags); in jz4740_rtc_ctrl_set_bits()
[all …]
/linux-6.12.1/sound/soc/codecs/
Dmax98373.c1 // SPDX-License-Identifier: GPL-2.0
23 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98373_dac_event()
28 regmap_update_bits(max98373->regmap, in max98373_dac_event()
34 regmap_update_bits(max98373->regmap, in max98373_dac_event()
38 max98373->tdm_mode = false; in max98373_dac_event()
85 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
101 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
102 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
103 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
104 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
[all …]
/linux-6.12.1/drivers/pci/controller/dwc/
Dpcie-fu740.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2019-2021 SiFive, Inc.
26 #include <linux/reset.h>
28 #include "pcie-designware.h"
30 #define to_fu740_pcie(x) dev_get_drvdata((x)->dev)
35 struct gpio_desc *reset; member
82 /* Assert PERST_N GPIO */ in fu740_pcie_assert_reset()
83 gpiod_set_value_cansleep(afp->reset, 0); in fu740_pcie_assert_reset()
84 /* Assert controller PERST_N */ in fu740_pcie_assert_reset()
85 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N); in fu740_pcie_assert_reset()
[all …]
Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
30 #include <linux/reset.h>
36 #include "pcie-designware.h"
58 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
86 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
108 int (*core_reset)(struct imx_pcie *pcie, bool assert);
143 /* PCIe Port Logic registers (memory-mapped) */
156 /* PHY registers (not memory-mapped) */
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
Ddcn31_hpo_dp_stream_encoder.c32 enc3->base.ctx->logger
35 (enc3->regs->reg)
39 enc3->hpo_se_shift->field_name, enc3->hpo_se_mask->field_name
42 enc3->base.ctx
69 /* Assert reset to the DP_SYM32_ENC logic */ in dcn31_hpo_dp_stream_enc_enable_stream()
72 /* Wait for reset to complete (to assert) */ in dcn31_hpo_dp_stream_enc_enable_stream()
77 /* De-assert reset to the DP_SYM32_ENC logic */ in dcn31_hpo_dp_stream_enc_enable_stream()
80 /* Wait for reset to de-assert */ in dcn31_hpo_dp_stream_enc_enable_stream()
104 /* Reset and Enable Pixel to Symbol FIFO */ in dcn31_hpo_dp_stream_enc_dp_unblank()
118 /* Reset and Enable Clock Ramp Adjuster FIFO */ in dcn31_hpo_dp_stream_enc_dp_unblank()
[all …]
/linux-6.12.1/drivers/phy/ralink/
Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/reset.h>
63 writel(val, phy->base + reg); in u2_phy_w32()
68 return readl(phy->base + reg); in u2_phy_r32()
97 regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, in ralink_usb_phy_power_on()
98 phy->clk, phy->clk); in ralink_usb_phy_power_on()
101 regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1, in ralink_usb_phy_power_on()
105 /* deassert the reset lines */ in ralink_usb_phy_power_on()
106 reset_control_deassert(phy->rsthost); in ralink_usb_phy_power_on()
107 reset_control_deassert(phy->rstdev); in ralink_usb_phy_power_on()
[all …]
/linux-6.12.1/drivers/macintosh/
Dmediabay.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2))
33 #define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r))
76 * Wait that number of ms between each step in normal polling mode
81 * Consider the media-bay ID value stable if it is the same for
86 /* Wait after powering up the media bay this delay in ms
92 * Hold the media-bay reset signal true for this many ticks
98 * Wait this long after the reset signal is released and before doing
99 * further operations. After this delay, the IDE reset signal is released
105 * Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted
[all …]
/linux-6.12.1/drivers/pps/clients/
Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
33 struct timer_list echo_timer; /* timer to reset echo active state */
55 rising_edge = gpiod_get_value(info->gpio_pin); in pps_gpio_irq_handler()
56 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
57 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
58 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
59 else if (info->capture_clear && in pps_gpio_irq_handler()
60 ((rising_edge && info->assert_falling_edge) || in pps_gpio_irq_handler()
[all …]
/linux-6.12.1/drivers/watchdog/
Dpnx4008_wdt.c1 // SPDX-License-Identifier: GPL-2.0
12 * 2005-2006 (c) MontaVista Software, Inc.
34 /* WatchDog Timer - Chapter 23 Page 207 */
87 /* stop counter, initiate counter reset */ in pnx4008_wdt_start()
89 /*wait for reset to complete. 100% guarantee event */ in pnx4008_wdt_start()
92 /* internal and external reset, stop after that */ in pnx4008_wdt_start()
98 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ in pnx4008_wdt_start()
100 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); in pnx4008_wdt_start()
121 wdd->timeout = new_timeout; in pnx4008_wdt_set_timeout()
133 * - For details, see the 'reboot' syscall in kernel/reboot.c in pnx4008_restart_handler()
[all …]
/linux-6.12.1/include/linux/
Drmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011-2016 Synaptics Incorporated
21 * struct rmi_2d_axis_alignment - target axis alignment
22 * @swap_axes: set to TRUE if desired to swap x- and y-axis
23 * @flip_x: set to TRUE if desired to flip direction on x-axis
24 * @flip_y: set to TRUE if desired to flip direction on y-axis
25 * @clip_x_low - reported X coordinates below this setting will be clipped to
27 * @clip_x_high - reported X coordinates above this setting will be clipped to
29 * @clip_y_low - reported Y coordinates below this setting will be clipped to
31 * @clip_y_high - reported Y coordinates above this setting will be clipped to
[all …]
Dmhi.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
10 #include <linux/dma-direction.h>
27 * enum mhi_callback - MHI callback
51 * enum mhi_flags - Transfer flags
63 * enum mhi_device_type - Device types
73 * enum mhi_ch_type - Channel types
89 * struct image_info - Firmware and RDDM table
102 * struct mhi_link_info - BW requirement
103 * target_link_speed - Link speed as defined by TLS bits in LinkControl reg
[all …]
/linux-6.12.1/drivers/ata/
Dahci_dwc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #define DRV_NAME "ahci-dwc"
95 /* Baikal-T1 AHCI SATA specific registers */
127 struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; in ahci_bt1_init()
134 dev_err(&dpriv->pdev->dev, "No system clocks specified\n"); in ahci_bt1_init()
135 return -EINVAL; in ahci_bt1_init()
139 * Fully reset the SATA AXI and ref clocks domain to ensure the state in ahci_bt1_init()
145 dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n"); in ahci_bt1_init()
151 dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n"); in ahci_bt1_init()
163 dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL); in ahci_dwc_get_resources()
[all …]
/linux-6.12.1/drivers/media/i2c/
Dadv7183.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
38 * All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
69 return &container_of(ctrl->handler, struct adv7183, hdl)->sd; in to_sd()
95 return -1; in adv7183_writeregs()
185 v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name); in adv7183_log_status()
193 *std = decoder->std; in adv7183_g_std()
220 return -EINVAL; in adv7183_s_std()
223 decoder->std = std; in adv7183_s_std()
[all …]
/linux-6.12.1/drivers/net/ethernet/chelsio/cxgb/
Dpm3393.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
87 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
93 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
97 /* Port reset. */
115 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
138 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
144 /* TERMINATOR - PL_INTERUPTS_EXT */ in pm3393_interrupt_enable()
145 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
[all …]

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