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/linux-6.12.1/Documentation/devicetree/bindings/regulator/
Danatop-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
25 anatop-vol-bit-shift:
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/linux-6.12.1/drivers/regulator/
Danatop-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <linux/regulator/driver.h>
16 #include <linux/regulator/of_regulator.h>
17 #include <linux/regulator/machine.h>
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
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/linux-6.12.1/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx-anatop.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
16 - items:
17 - enum:
18 - fsl,imx6sl-anatop
19 - fsl,imx6sll-anatop
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/linux-6.12.1/drivers/cpufreq/
Dimx6q-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/nvmem-consumer.h>
16 #include <linux/regulator/consumer.h>
24 static struct regulator *arm_reg;
25 static struct regulator *pu_reg;
26 static struct regulator *soc_reg;
83 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", in imx6q_set_target()
92 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); in imx6q_set_target()
116 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it in imx6q_set_target()
117 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it in imx6q_set_target()
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/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6sl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
51 #size-cells = <0>;
54 compatible = "arm,cortex-a9";
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Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
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