Searched +full:rcar +full:- +full:gen3 +full:- +full:drif (Results 1 – 8 of 8) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/media/renesas,drif.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general15 representation of DRIF interfacing with a master device is shown below.17 +---------------------+ +---------------------+[all …]
1 # SPDX-License-Identifier: GPL-2.0-only18 tristate "R-Car MIPI CSI-2 Receiver"27 Support for Renesas R-Car MIPI CSI-2 receiver.28 Supports R-Car Gen3 and RZ/G2 SoCs.31 module will be called rcar-csi2.34 tristate "R-Car Image Signal Processor (ISP)"43 Support for Renesas R-Car Image Signal Processor (ISP).44 Enable this to support the Renesas R-Car Image Signal48 module will be called rcar-isp.59 source "drivers/media/platform/renesas/rcar-vin/Kconfig"[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * R-Car Gen3 Digital Radio Interface (DRIF) driver9 * The R-Car DRIF is a receive only MSIOF like controller with an11 * then this driver uses the SYS-DMAC engine to move the data from14 * Each DRIF channel DRIFx (as per datasheet) contains two internal21 * Depending on the master device, a DRIF channel can use29 * framework. This driver expects a tuner driver (sub-device) to bind31 * a V4L2 compliant SDR device. The DRIF driver is independent of the34 * The DRIF h/w can support I2S mode and Frame start synchronization pulse mode.36 * suitable master devices. Hence, not all configurable options of DRIF h/w[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car E3 (R8A77990) SoC5 * Copyright (C) 2018-2019 Renesas Electronics Corp.8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/power/r8a77990-sysc.h>14 #address-cells = <2>;15 #size-cells = <2>;23 compatible = "fixed-clock";24 #clock-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car M3-N (R8A77965) SoC11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>12 #include <dt-bindings/interrupt-controller/arm-gic.h>13 #include <dt-bindings/power/r8a77965-sysc.h>19 #address-cells = <2>;20 #size-cells = <2>;28 compatible = "fixed-clock";29 #clock-cells = <0>;30 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car M3-W (R8A77960) SoC5 * Copyright (C) 2016-2017 Renesas Electronics Corp.8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/power/r8a7796-sysc.h>14 #address-cells = <2>;15 #size-cells = <2>;23 compatible = "fixed-clock";24 #clock-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car H3 (R8A77951) SoC8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/power/r8a7795-sysc.h>19 #address-cells = <2>;20 #size-cells = <2>;28 compatible = "fixed-clock";29 #clock-cells = <0>;30 clock-frequency = <0>;[all …]
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-scsi@vger.kernel.org88 F: drivers/scsi/3w-*[all …]