Searched full:r2p0 (Results 1 – 14 of 14) sorted by relevance
| /linux-6.12.1/arch/arm/include/asm/hardware/ |
| D | cache-l2x0.h | 118 #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
119 #define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
120 #define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
125 #define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
130 #define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/ |
| D | arm,scu.yaml | 19 Revision r2p0
23 Manial Revision r2p0
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| /linux-6.12.1/arch/arm/mm/ |
| D | cache-tauros3.h | 16 * but with PREFETCH_CTRL (r2p0) and an additional event counter.
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| D | proc-v7.S | 335 teq r6, #0x20 @ only present in r2p0
342 teq r6, #0x20 @ only present in r2p0
358 teq r6, #0x20 @ present in r2p0
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| D | Kconfig | 1014 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
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| D | cache-l2x0.c | 439 * 588369: PL310 R0P0->R1P0, fixed R2P0.
447 * 727915: PL310 R2P0->R3P0, fixed R3P1.
557 /* From r2p0, there is Prefetch offset/control register */ in l2c310_save()
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| /linux-6.12.1/Documentation/devicetree/bindings/timer/ |
| D | arm,global_timer.yaml | 22 description: driver supports versions r2p0 and above.
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| /linux-6.12.1/arch/arm64/kernel/ |
| D | cpu_errata.c | 300 * - 1188873 affects r0p0 to r2p0
346 /* Cortex A76 r0p0 to r2p0 */
354 /* Cortex A55 r0p0 to r2p0 */
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| /linux-6.12.1/arch/arm/kernel/ |
| D | smp_scu.c | 58 /* Cortex-A9 earlier than r2p0 has no standby bit in SCU */ in scu_enable()
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| /linux-6.12.1/arch/arm/ |
| D | Kconfig | 576 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
592 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
624 (r2p0..r2p2) erratum. Under certain conditions, specific to the
652 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
706 r2p0) erratum. The Store Buffer does not have any automatic draining
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| /linux-6.12.1/drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu-impl.c | 115 * On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before in arm_mmu500_reset()
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| /linux-6.12.1/drivers/spi/ |
| D | spi-sprd-adi.c | 54 * ADI supports 12/14bit address for r2p0, and additional 17bit for r3p0 or
82 * REG_ADI_RD_CMD bit[14:0] for r2p0
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| /linux-6.12.1/drivers/clocksource/ |
| D | arm_global_timer.c | 349 * In A9 r2p0 the comparators for each processor with the global timer in global_timer_of_register()
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| /linux-6.12.1/arch/arm64/ |
| D | Kconfig | 675 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
701 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
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