Searched +full:queue +full:- +full:txready (Results 1 – 25 of 25) sorted by relevance
/linux-6.12.1/Documentation/devicetree/bindings/net/ |
D | intel,ixp4xx-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - $ref: ethernet-controller.yaml# 14 - Linus Walleij <linus.walleij@linaro.org> 18 Processing Engine) and the IXP4xx Queue Manager to process 24 const: intel,ixp4xx-ethernet 30 queue-rx: 31 $ref: /schemas/types.yaml#/definitions/phandle-array [all …]
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D | intel,ixp4xx-hss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Linus Walleij <linus.walleij@linaro.org> 15 Processing Engine) and the IXP4xx Queue Manager to process 20 const: intel,ixp4xx-hss 26 intel,npe-handle: 27 $ref: /schemas/types.yaml#/definitions/phandle-array 30 - description: phandle to the NPE this HSS instance is using [all …]
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/linux-6.12.1/arch/arm/boot/dts/intel/ixp/ |
D | intel-ixp45x-ixp46x.dtsi | 1 // SPDX-License-Identifier: ISC 8 #include "intel-ixp4xx.dtsi" 13 compatible = "intel,ixp46x-expansion-bus-controller", "syscon"; 19 compatible = "intel,ixp46x-rng"; 23 interrupt-controller@c8003000 { 24 compatible = "intel,ixp43x-interrupt"; 32 compatible = "intel,ixp4xx-udc"; 39 compatible = "intel,ixp4xx-i2c"; 47 compatible = "intel,ixp4xx-ethernet"; 52 queue-rx = <&qmgr 0>; [all …]
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D | intel-ixp4xx.dtsi | 1 // SPDX-License-Identifier: ISC 6 #include <dt-bindings/interrupt-controller/irq.h> 7 #include <dt-bindings/gpio/gpio.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 14 compatible = "simple-bus"; 15 interrupt-parent = <&intcon>; 22 /* compatible and reg filled in by per-soc device tree */ 23 native-endian; 24 #address-cells = <2>; [all …]
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D | intel-ixp42x-goramo-multilink.dts | 1 // SPDX-License-Identifier: ISC 5 * - MultiLink Basic (a box) 6 * - MultiLink Max (19" rack mount) 9 * This is one of the few devices supporting the IXP4xx High-Speed Serial 14 /dts-v1/; 16 #include "intel-ixp42x.dtsi" 17 #include <dt-bindings/input/input.h> 21 compatible = "goramo,multilink-router", "intel,ixp42x"; 22 #address-cells = <1>; 23 #size-cells = <1>; [all …]
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D | intel-ixp43x-kixrp435.dts | 1 // SPDX-License-Identifier: ISC 7 /dts-v1/; 9 #include "intel-ixp43x.dtsi" 10 #include "intel-ixp4xx-reference-design.dtsi" 11 #include <dt-bindings/input/input.h> 16 #address-cells = <1>; 17 #size-cells = <1>; 22 compatible = "intel,ixp4xx-flash", "cfi-flash"; 23 bank-width = <2>; 25 intel,ixp4xx-eb-write-enable = <1>; [all …]
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D | intel-ixp42x-ixdp425.dts | 1 // SPDX-License-Identifier: ISC 11 /dts-v1/; 13 #include "intel-ixp42x.dtsi" 14 #include "intel-ixp4xx-reference-design.dtsi" 15 #include <dt-bindings/input/input.h> 20 #address-cells = <1>; 21 #size-cells = <1>; 26 compatible = "intel,ixp4xx-flash", "cfi-flash"; 27 bank-width = <2>; 29 intel,ixp4xx-eb-write-enable = <1>; [all …]
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D | intel-ixp42x-gateway-7001.dts | 1 // SPDX-License-Identifier: ISC 7 /dts-v1/; 9 #include "intel-ixp42x.dtsi" 10 #include <dt-bindings/input/input.h> 15 #address-cells = <1>; 16 #size-cells = <1>; 26 stdout-path = "uart1:115200n8"; 37 compatible = "intel,ixp4xx-flash", "cfi-flash"; 38 bank-width = <2>; 45 intel,ixp4xx-eb-write-enable = <1>; [all …]
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D | intel-ixp42x-adi-coyote.dts | 1 // SPDX-License-Identifier: ISC 5 * Ethernet set-up from OpenWrt. 8 /dts-v1/; 10 #include "intel-ixp42x.dtsi" 11 #include <dt-bindings/input/input.h> 16 #address-cells = <1>; 17 #size-cells = <1>; 27 stdout-path = "uart1:115200n8"; 39 compatible = "intel,ixp4xx-flash", "cfi-flash"; 40 bank-width = <2>; [all …]
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D | intel-ixp42x-ixdpg425.dts | 1 // SPDX-License-Identifier: ISC 5 * Ethernet set-up from OpenWrt. 15 /dts-v1/; 17 #include "intel-ixp42x.dtsi" 18 #include <dt-bindings/input/input.h> 23 #address-cells = <1>; 24 #size-cells = <1>; 34 stdout-path = "uart0:115200n8"; 44 compatible = "intel,ixp4xx-flash", "cfi-flash"; 45 bank-width = <2>; [all …]
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D | intel-ixp42x-linksys-wrv54g.dts | 1 // SPDX-License-Identifier: ISC 9 /dts-v1/; 11 #include "intel-ixp42x.dtsi" 12 #include <dt-bindings/input/input.h> 17 #address-cells = <1>; 18 #size-cells = <1>; 28 stdout-path = "uart1:115200n8"; 39 compatible = "gpio-leds"; 40 led-power { 43 default-state = "on"; [all …]
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D | intel-ixp42x-arcom-vulcan.dts | 1 // SPDX-License-Identifier: ISC 8 /dts-v1/; 10 #include "intel-ixp42x.dtsi" 11 #include <dt-bindings/input/input.h> 16 #address-cells = <1>; 17 #size-cells = <1>; 27 stdout-path = "uart0:115200n8"; 35 compatible = "w1-gpio"; 42 compatible = "intel,ixp4xx-flash", "cfi-flash"; 43 bank-width = <2>; [all …]
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D | intel-ixp42x-gateworks-gw2348.dts | 1 // SPDX-License-Identifier: ISC 7 /dts-v1/; 9 #include "intel-ixp42x.dtsi" 10 #include <dt-bindings/input/input.h> 15 #address-cells = <1>; 16 #size-cells = <1>; 25 stdout-path = "uart0:115200n8"; 33 compatible = "gpio-leds"; 34 led-user { 37 default-state = "on"; [all …]
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D | intel-ixp42x-freecom-fsg-3.dts | 1 // SPDX-License-Identifier: ISC 3 * Device Tree file for the Freecom FSG-3 router. 8 /dts-v1/; 10 #include "intel-ixp42x.dtsi" 11 #include <dt-bindings/input/input.h> 14 model = "Freecom FSG-3"; 15 compatible = "freecom,fsg-3", "intel,ixp42x"; 16 #address-cells = <1>; 17 #size-cells = <1>; 28 stdout-path = "uart0:115200n8"; [all …]
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D | intel-ixp42x-usrobotics-usr8200.dts | 1 // SPDX-License-Identifier: ISC 4 * VPN and NAS. Based on know-how from Peter Denison. 10 /dts-v1/; 12 #include "intel-ixp42x.dtsi" 13 #include <dt-bindings/input/input.h> 18 #address-cells = <1>; 19 #size-cells = <1>; 28 stdout-path = "uart1:115200n8"; 38 compatible = "gpio-leds"; 39 ieee1394_led: led-1394 { [all …]
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D | intel-ixp43x-gateworks-gw2358.dts | 1 // SPDX-License-Identifier: ISC 3 * Device Tree file for Gateworks IXP43x-based Cambria GW2358 6 /dts-v1/; 8 #include "intel-ixp43x.dtsi" 13 #address-cells = <1>; 14 #size-cells = <1>; 24 stdout-path = "uart0:115200n8"; 32 compatible = "gpio-leds"; 33 led-user { 36 default-state = "on"; [all …]
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D | intel-ixp42x-welltech-epbx100.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 #include "intel-ixp42x.dtsi" 13 #address-cells = <1>; 14 #size-cells = <1>; 24 stdout-path = "uart0:115200n8"; 34 compatible = "intel,ixp4xx-flash", "cfi-flash"; 35 bank-width = <2>; 42 compatible = "fixed-partitions"; 43 #address-cells = <1>; [all …]
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D | intel-ixp42x-netgear-wg302v1.dts | 1 // SPDX-License-Identifier: ISC 7 /dts-v1/; 9 #include "intel-ixp42x.dtsi" 10 #include <dt-bindings/input/input.h> 15 #address-cells = <1>; 16 #size-cells = <1>; 27 stdout-path = "uart1:9600n8"; 38 compatible = "intel,ixp4xx-flash", "cfi-flash"; 39 bank-width = <2>; 47 intel,ixp4xx-eb-write-enable = <1>; [all …]
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D | intel-ixp42x-iomega-nas100d.dts | 1 // SPDX-License-Identifier: ISC 6 /dts-v1/; 8 #include "intel-ixp42x.dtsi" 9 #include <dt-bindings/input/input.h> 13 compatible = "iom,nas-100d", "intel,ixp42x"; 14 #address-cells = <1>; 15 #size-cells = <1>; 25 stdout-path = "uart0:115200n8"; 33 compatible = "gpio-leds"; 34 led-wlan { [all …]
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D | intel-ixp42x-linksys-nslu2.dts | 1 // SPDX-License-Identifier: ISC 6 /dts-v1/; 8 #include "intel-ixp42x.dtsi" 9 #include <dt-bindings/input/input.h> 14 #address-cells = <1>; 15 #size-cells = <1>; 25 stdout-path = "uart0:115200n8"; 33 compatible = "gpio-leds"; 34 led-status { 37 default-state = "on"; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/crypto/ |
D | intel,ixp4xx-crypto.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Linus Walleij <linus.walleij@linaro.org> 21 const: intel,ixp4xx-crypto 23 intel,npe-handle: 24 $ref: /schemas/types.yaml#/definitions/phandle-array 26 - items: 27 - description: phandle to the NPE this crypto engine [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/firmware/ |
D | intel,ixp4xx-network-processing-engine.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Linus Walleij <linus.walleij@linaro.org> 24 - items: 25 - const: intel,ixp4xx-network-processing-engine 29 - description: NPE0 (NPE-A) register range 30 - description: NPE1 (NPE-B) register range 31 - description: NPE2 (NPE-C) register range [all …]
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/linux-6.12.1/drivers/net/ethernet/xscale/ |
D | ixp4xx_eth.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) 12 * TX queue 23 24 25 13 * RX-free queue 26 27 28 14 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable 16 * Queue entries: 17 * bits 0 -> 1 - NPE ID (RX and TX-done) 18 * bits 0 -> 2 - priority (TX, per 802.1D) 19 * bits 3 -> 4 - port ID (user-set?) 20 * bits 5 -> 31 - physical descriptor address [all …]
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/linux-6.12.1/drivers/net/wan/ |
D | ixp4xx_hss.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl> 13 #include <linux/dma-mapping.h> 60 /* Queue IDs */ 90 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */ 142 /* 56k data endiannes - which bit unused: high (default) or low */ 180 * The clock sequence consists of (C - B) states of 0s and 1s, each state is 192 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits 201 #define TDMMAP_HDLC 1 /* HDLC - packetized */ 202 #define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */ [all …]
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/linux-6.12.1/drivers/crypto/intel/ixp4xx/ |
D | ixp4xx_crypto.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Intel IXP4xx NPE-C crypto driver 9 #include <linux/dma-mapping.h> 34 /* Intermittent includes, delete this after v5.14-rc1 */ 239 return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl); in crypt_virt2phys() 244 return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl); in crypt_phys2virt() 249 return container_of(tfm->__crt_alg, struct ixp_alg, crypto.base)->cfg_enc; in cipher_cfg_enc() 254 return container_of(tfm->__crt_alg, struct ixp_alg, crypto.base)->cfg_dec; in cipher_cfg_dec() 259 return container_of(tfm->__crt_alg, struct ixp_alg, crypto.base)->hash; in ix_hash() 264 struct device *dev = &pdev->dev; in setup_crypt_desc() [all …]
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