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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dqcom,spi-qcom-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 description: The QSPI controller allows SPI protocol communication in single,
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
23 - qcom,sc7180-qspi
[all …]
/linux-6.12.1/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10_socdk_qspi.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 &qspi {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "micron,mt25qu02g", "jedec,spi-nor";
17 spi-max-frequency = <100000000>;
19 m25p,fast-read;
20 cdns,read-delay = <3>;
21 cdns,tshsl-ns = <50>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/xilinx/
Dzynqmp-zcu1275-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
23 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
45 &qspi {
48 compatible = "m25p80", "jedec,spi-nor";
50 spi-tx-bus-width = <4>;
[all …]
Dzynqmp-zc1254-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
18 compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
23 spi0 = &qspi;
28 stdout-path = "serial0:115200n8";
41 &qspi {
44 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
45 #address-cells = <1>;
[all …]
Dzynqmp-zc1232-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
22 spi0 = &qspi;
27 stdout-path = "serial0:115200n8";
40 &qspi {
43 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
44 #address-cells = <1>;
[all …]
Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
29 spi0 = &qspi;
34 stdout-path = "serial0:115200n8";
117 phy-mode = "rgmii-id";
[all …]
/linux-6.12.1/arch/mips/boot/dts/brcm/
Dbcm7420.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <93750000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
Dbcm97358svmb.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "bcm97xxx-nand-cs1-bch4.dtsi"
18 stdout-path = &uart0;
78 &qspi {
84 spi-max-frequency = <40000000>;
85 spi-cpol;
86 spi-cpha;
87 use-bspi;
88 m25p,fast-read;
[all …]
Dbcm97360svmb.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
17 stdout-path = &uart0;
81 &qspi {
87 spi-max-frequency = <40000000>;
88 spi-cpol;
89 spi-cpha;
90 use-bspi;
91 m25p,fast-read;
94 compatible = "fixed-partitions";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amd/
Delba-asic.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 * Copyright 2020-2022 Advanced Micro Devices, Inc.
8 /dts-v1/;
11 #include "elba-16core.dtsi"
12 #include "elba-asic-common.dtsi"
13 #include "elba-flash-parts.dtsi"
17 compatible = "amd,pensando-elba-ortano", "amd,pensando-elba";
22 spi1 = &qspi;
26 stdout-path = "serial0:115200n8";
/linux-6.12.1/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2g-ice.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
26 dsp_common_memory: dsp-common-memory@81f800000 {
[all …]
Dkeystone-k2g-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
12 compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
20 reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
25 dsp_common_memory: dsp-common-memory@81f800000 {
26 compatible = "shared-dma-pool";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1012a-frwy.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "fsl-ls1012a.dtsi"
16 compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
31 &qspi {
35 compatible = "jedec,spi-nor";
36 #address-cells = <1>;
37 #size-cells = <1>;
38 m25p,fast-read;
39 spi-max-frequency = <50000000>;
[all …]
Dfsl-ls1012a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "fsl-ls1012a.dtsi"
15 compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
29 sd-uhs-sdr104;
30 sd-uhs-sdr50;
31 sd-uhs-sdr25;
32 sd-uhs-sdr12;
37 mmc-hs200-1_8v;
[all …]
Dfsl-ls2081a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls2088a.dtsi"
17 compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
25 stdout-path = "serial1:115200n8";
33 compatible = "jedec,spi-nor";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 spi-max-frequency = <3000000>;
51 #address-cells = <1>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Dam437x-idk-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
9 #include <dt-bindings/pinctrl/am43xx.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
19 stdout-path = &uart0;
22 v24_0d: fixed-regulator-v24_0d {
[all …]
Ddra72-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "dra7-ipu-dsp-common.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/clock/ti-dra7-atl.h>
13 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
20 stdout-path = &uart1;
23 evm_12v0: fixedregulator-evm12v0 {
25 compatible = "regulator-fixed";
[all …]
Dam574x-idk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
10 #include "dra7-mmc-iodelay.dtsi"
11 #include "dra76x-mmc-iodelay.dtsi"
12 #include "am572x-idk-common.dtsi"
16 compatible = "ti,am5748-idk", "ti,am5748", "ti,dra762", "ti,dra7";
19 &qspi {
20 spi-max-frequency = <96000000>;
22 spi-max-frequency = <96000000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dstm32mp157c-phycore-stm32mp1-3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
7 /dts-v1/;
9 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
12 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include "stm32mp157c-phycore-stm32mp15-som.dtsi"
16 model = "PHYTEC phyCORE-STM32MP1-3 Dev Board";
17 compatible = "phytec,phycore-stm32mp1-3",
18 "phytec,phycore-stm32mp157c-som", "st,stm32mp157";
54 &qspi {
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dat91-sam9x60ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
14 model = "Microchip SAM9X60-EK";
24 stdout-path = "serial0:115200n8";
29 clock-frequency = <32768>;
33 clock-frequency = <24000000>;
37 gpio-keys {
38 compatible = "gpio-keys";
[all …]
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr8a7792-wheat.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
24 stdout-path = "serial0:115200n8";
32 d1_8v: regulator-1v8 {
33 compatible = "regulator-fixed";
34 regulator-name = "D1.8V";
35 regulator-min-microvolt = <1800000>;
36 regulator-max-microvolt = <1800000>;
[all …]
Dr8a7790-stout.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
32 compatible = "gpio-leds";
47 fixedregulator1v8: regulator-1v8 {
48 compatible = "regulator-fixed";
49 regulator-name = "fixed-1.8V";
50 regulator-min-microvolt = <1800000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm53340-ubnt-unifi-switch8.dts9 /dts-v1/;
11 #include "bcm-hr2.dtsi"
14 compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2";
33 &qspi {
35 bspi-sel = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 spi-max-frequency = <12500000>;
43 spi-cpol;
44 spi-cpha;
[all …]
/linux-6.12.1/arch/arm/boot/dts/mediatek/
Dmt7629-rfb.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
26 button-reset {
32 button-wps {
44 reg_3p3v: regulator-3p3v {
[all …]
/linux-6.12.1/drivers/spi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
155 supports spi-mem interface.
234 this code to manage the per-word or per-transfer accesses to the
263 Cadence QSPI is a specialized controller for connecting an SPI
[all …]

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