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/linux-6.12.1/arch/arm64/boot/dts/microchip/
Dsparx5_pcb135_board.dtsi369 phy-mode = "qsgmii";
376 phy-mode = "qsgmii";
383 phy-mode = "qsgmii";
390 phy-mode = "qsgmii";
397 phy-mode = "qsgmii";
404 phy-mode = "qsgmii";
411 phy-mode = "qsgmii";
418 phy-mode = "qsgmii";
425 phy-mode = "qsgmii";
432 phy-mode = "qsgmii";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1043a-tqmls1043a-mbls10xxa.dts22 qsgmii-s1-p1 = &qsgmii1_phy1;
23 qsgmii-s1-p2 = &qsgmii1_phy2;
24 qsgmii-s1-p3 = &qsgmii1_phy3;
25 qsgmii-s1-p4 = &qsgmii1_phy4;
26 qsgmii-s2-p1 = &qsgmii2_phy1;
27 qsgmii-s2-p2 = &qsgmii2_phy2;
28 qsgmii-s2-p3 = &qsgmii2_phy3;
29 qsgmii-s2-p4 = &qsgmii2_phy4;
Dfsl-ls1046a-tqmls1046a-mbls10xxa.dts21 qsgmii-s1-p1 = &qsgmii1_phy1;
22 qsgmii-s1-p2 = &qsgmii1_phy2;
23 qsgmii-s1-p3 = &qsgmii1_phy3;
24 qsgmii-s1-p4 = &qsgmii1_phy4;
25 qsgmii-s2-p1 = &qsgmii2_phy1;
26 qsgmii-s2-p2 = &qsgmii2_phy2;
27 qsgmii-s2-p3 = &qsgmii2_phy3;
28 qsgmii-s2-p4 = &qsgmii2_phy4;
Dfsl-ls1088a-tqmls1088a-mbls10xxa.dts32 qsgmii-s1-p1 = &qsgmii1_phy1;
33 qsgmii-s1-p2 = &qsgmii1_phy2;
34 qsgmii-s1-p3 = &qsgmii1_phy3;
35 qsgmii-s1-p4 = &qsgmii1_phy4;
36 qsgmii-s2-p1 = &qsgmii2_phy1;
37 qsgmii-s2-p2 = &qsgmii2_phy2;
38 qsgmii-s2-p3 = &qsgmii2_phy3;
39 qsgmii-s2-p4 = &qsgmii2_phy4;
Dfsl-ls1088a-rdb.dts28 phy-connection-type = "qsgmii";
35 phy-connection-type = "qsgmii";
42 phy-connection-type = "qsgmii";
49 phy-connection-type = "qsgmii";
56 phy-connection-type = "qsgmii";
63 phy-connection-type = "qsgmii";
70 phy-connection-type = "qsgmii";
77 phy-connection-type = "qsgmii";
Dfsl-ls1028a-kontron-kbox-a-230-ls.dts40 /* BCM54140 QSGMII quad PHY */
86 phy-mode = "qsgmii";
96 phy-mode = "qsgmii";
106 phy-mode = "qsgmii";
116 phy-mode = "qsgmii";
Dfsl-ls1043a-qds.dts31 qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
32 qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
33 qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
34 qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
35 qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
36 qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
37 qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
38 qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
Dfsl-ls1028a-qds-65bb.dtso57 phy-mode = "qsgmii";
64 phy-mode = "qsgmii";
71 phy-mode = "qsgmii";
78 phy-mode = "qsgmii";
Dfsl-ls1028a-qds-85bb.dtso57 phy-mode = "qsgmii";
64 phy-mode = "qsgmii";
71 phy-mode = "qsgmii";
78 phy-mode = "qsgmii";
Dfsl-ls1088a-ten64.dts111 phy-connection-type = "qsgmii";
118 phy-connection-type = "qsgmii";
125 phy-connection-type = "qsgmii";
132 phy-connection-type = "qsgmii";
140 phy-connection-type = "qsgmii";
147 phy-connection-type = "qsgmii";
154 phy-connection-type = "qsgmii";
161 phy-connection-type = "qsgmii";
Dfsl-ls1043-post.dtsi27 pcs-handle-names = "qsgmii";
33 pcs-handle-names = "sgmii", "qsgmii";
45 pcs-handle-names = "sgmii", "qsgmii";
51 pcs-handle-names = "sgmii", "qsgmii";
Dfsl-ls1046-post.dtsi28 pcs-handle-names = "qsgmii";
43 pcs-handle-names = "sgmii", "qsgmii";
49 pcs-handle-names = "sgmii", "qsgmii";
58 pcs-handle-names = "sgmii", "qsgmii", "xfi";
Dfsl-ls1046a-frwy.dts128 phy-connection-type = "qsgmii";
133 phy-connection-type = "qsgmii";
138 phy-connection-type = "qsgmii";
143 phy-connection-type = "qsgmii";
Dfsl-ls1028a-rdb.dts128 /* VSC8514 QSGMII quad PHY */
290 phy-mode = "qsgmii";
298 phy-mode = "qsgmii";
306 phy-mode = "qsgmii";
314 phy-mode = "qsgmii";
Dfsl-ls1043a-rdb.dts159 phy-connection-type = "qsgmii";
164 phy-connection-type = "qsgmii";
179 phy-connection-type = "qsgmii";
184 phy-connection-type = "qsgmii";
/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/
Dmscc,ocelot.yaml33 - phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
52 - phy-mode = "qsgmii": on ports 0, 1, 2, 3
112 phy-mode = "qsgmii";
119 phy-mode = "qsgmii";
126 phy-mode = "qsgmii";
133 phy-mode = "qsgmii";
181 phy-mode = "qsgmii";
188 phy-mode = "qsgmii";
195 phy-mode = "qsgmii";
202 phy-mode = "qsgmii";
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dti,phy-gmii-sel.yaml65 ti,qsgmii-main-ports:
68 Required only for QSGMII mode. Array to select the port/s for QSGMII
69 main mode. The size of the array corresponds to the number of QSGMII
70 interfaces and thus, the number of distinct QSGMII main ports,
71 supported by the device. If the device supports two QSGMII interfaces
72 but only one QSGMII interface is desired, repeat the QSGMII main port
73 value corresponding to the QSGMII interface in the array.
106 ti,qsgmii-main-ports:
121 ti,qsgmii-main-ports:
139 ti,qsgmii-main-ports: false
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dt1040rdb.dts68 /* VSC8514 QSGMII PHY */
85 /* VSC8514 QSGMII PHY */
121 phy-mode = "qsgmii";
129 phy-mode = "qsgmii";
137 phy-mode = "qsgmii";
145 phy-mode = "qsgmii";
153 phy-mode = "qsgmii";
161 phy-mode = "qsgmii";
169 phy-mode = "qsgmii";
177 phy-mode = "qsgmii";
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-j7200-evm-quad-port-eth-exp.dtso3 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
33 phy-mode = "qsgmii";
41 phy-mode = "qsgmii";
49 phy-mode = "qsgmii";
57 phy-mode = "qsgmii";
86 qsgmii-line-hog {
90 line-name = "qsgmii-pwrdn-line";
Dk3-j721e-evm-quad-port-eth-exp.dtso3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
35 phy-mode = "qsgmii";
43 phy-mode = "qsgmii";
51 phy-mode = "qsgmii";
59 phy-mode = "qsgmii";
88 qsgmii-line-hog {
92 line-name = "qsgmii-pwrdn-line";
Dk3-j784s4-evm-quad-port-eth-exp1.dtso3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
9 * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM
40 phy-mode = "qsgmii";
49 phy-mode = "qsgmii";
58 phy-mode = "qsgmii";
67 phy-mode = "qsgmii";
100 qsgmii-line-hog {
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dlan966x-pcb8290.dts119 phy-mode = "qsgmii";
127 phy-mode = "qsgmii";
135 phy-mode = "qsgmii";
143 phy-mode = "qsgmii";
151 phy-mode = "qsgmii";
159 phy-mode = "qsgmii";
167 phy-mode = "qsgmii";
175 phy-mode = "qsgmii";
Dlan966x-kontron-kswitch-d10-mmt.dtsi171 phy-mode = "qsgmii";
178 phy-mode = "qsgmii";
185 phy-mode = "qsgmii";
192 phy-mode = "qsgmii";
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dipq806x-dwmac.txt15 - qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
16 qsgmii-csr registers.
28 qcom,qsgmii-csr = <&qsgmii_csr>;
Dqcom,qca807x.yaml18 They feature 2 SerDes, one for PSGMII or QSGMII connection with
49 Option 3 QSGMII for copper SGMII for
56 - qsgmii
147 qcom,package-mode = "qsgmii";

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