Searched +full:qsgmii +full:- +full:main +full:- +full:ports (Results 1 – 6 of 6) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/4 ---5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#11 - Kishon Vijay Abraham I <kishon@ti.com>15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.20 +--------------+21 +-------------------------------+ |SCM |22 | CPSW | | +---------+ |[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/7 * Based on cpsw-phy-sel.c driver created by Mugunthan V N <mugunthanvnm@ti.com>31 #define PHY_GMII_PORT(n) BIT((n) - 1)73 const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data; in phy_gmii_sel_mode()74 struct device *dev = if_phy->priv->dev; in phy_gmii_sel_mode()80 return -EINVAL; in phy_gmii_sel_mode()104 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_QSGMII))) in phy_gmii_sel_mode()106 if (if_phy->priv->qsgmii_main_ports & BIT(if_phy->id - 1)) in phy_gmii_sel_mode()113 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII))) in phy_gmii_sel_mode()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/mux/mux.h>9 #include <dt-bindings/phy/phy.h>10 #include <dt-bindings/phy/phy-ti.h>12 #include "k3-serdes.h"15 serdes_refclk: clock-serdes {16 #clock-cells = <0>;17 compatible = "fixed-clock";[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT3 * Device Tree Source for J7200 SoC Family Main Domain peripherals5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/9 serdes_refclk: serdes-refclk {10 #clock-cells = <0>;11 compatible = "fixed-clock";17 compatible = "mmio-sram";19 #address-cells = <1>;20 #size-cells = <1>;23 atf-sram@0 {[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT3 * Device Tree Source for J721E SoC Family Main Domain peripherals5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy.h>8 #include <dt-bindings/phy/phy-ti.h>9 #include <dt-bindings/mux/mux.h>11 #include "k3-serdes.h"14 cmn_refclk: clock-cmnrefclk {15 #clock-cells = <0>;16 compatible = "fixed-clock";[all …]
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>153 * bit 30 = TX_ERR_SUM, one bit for 4 ports154 * bit 31 = MISC_SUM, one bit for 4 ports156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)270 * to cover all rate-limit values from 10Kbps up to 5Gbps296 (((index) < (q)->last_desc) ? ((index) + 1) : 0)374 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)377 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)486 /* Pointer to the CPU-local NAPI struct */[all …]