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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dintel,ixp46x-ptp-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp46x-ptp-timer.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP46x PTP Timer (TSYNC)
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP46x PTP timer is known in the manual as IEEE1588 Hardware
15 Assist and Time Synchronization Hardware Assist TSYNC provides a PTP
16 timer. It exists in the Intel IXP45x and IXP46x XScale SoCs.
20 const: intel,ixp46x-ptp-timer
[all …]
Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
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Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
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/linux-6.12.1/include/linux/fsl/
Dptp_qoriq.h1 // SPDX-License-Identifier: GPL-2.0
14 * qoriq ptp registers
17 u32 tmr_ctrl; /* Timer control register */
19 u32 tmr_temask; /* Timer event mask register */
21 u32 tmr_pemask; /* Timer event mask register */
23 u32 tmr_cnt_h; /* Timer counter high register */
24 u32 tmr_cnt_l; /* Timer counter low register */
25 u32 tmr_add; /* Timer drift compensation addend register */
26 u32 tmr_acc; /* Timer accumulator register */
27 u32 tmr_prsc; /* Timer prescale */
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dclock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
37 #include <rdma/mlx5-abi.h>
76 MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MIN = -200000,
111 * dev_freq_khz = 2^(shift_constant - 16) in mlx5_ptp_shift_constant()
122 static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp) in mlx5_ptp_getmaxphase() argument
124 struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); in mlx5_ptp_getmaxphase()
136 s64 max = mlx5_ptp_getmaxphase(&mdev->clock.ptp_info); in mlx5_is_mtutc_time_adj_cap()
138 if (delta < -max || delta > max) in mlx5_is_mtutc_time_adj_cap()
149 return -EOPNOTSUPP; in mlx5_set_mtutc()
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Dclock.h14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
62 return mdev->clock.ptp ? ptp_clock_index(mdev->clock.ptp) : -1; in mlx5_clock_get_ptp_index()
68 struct mlx5_timer *timer = &clock->timer; in mlx5_timecounter_cyc2time() local
73 seq = read_seqbegin(&clock->lock); in mlx5_timecounter_cyc2time()
74 nsec = timecounter_cyc2time(&timer->tc, timestamp); in mlx5_timecounter_cyc2time()
75 } while (read_seqretry(&clock->lock, seq)); in mlx5_timecounter_cyc2time()
94 return -1; in mlx5_clock_get_ptp_index()
/linux-6.12.1/Documentation/devicetree/bindings/ptp/
Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ptp/fsl,ptp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
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/linux-6.12.1/drivers/net/ethernet/freescale/
Dfec_ptp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Fast Ethernet Controller (ENET) PTP driver for MX6x.
94 * fec_ptp_read - read raw cycle counter (to be used by time counter)
107 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
109 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
111 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) in fec_ptp_read()
114 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
122 * This function enble the PPS ouput on the timer channel.
131 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
133 if (fep->pps_enable == enable) { in fec_ptp_enable_pps()
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/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Dstmmac_ptp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 PTP Header file
18 /* IEEE 1588 PTP register offsets */
20 #define PTP_SSIR 0x04 /* Sub-Second Increment Reg */
27 #define PTP_ATNR 0x48 /* Auxiliary Timestamp - Nanoseconds Reg */
28 #define PTP_ATSR 0x4c /* Auxiliary Timestamp - Seconds Reg */
37 #define PTP_DIGITAL_ROLLOVER_MODE 0x3B9ACA00 /* 10e9-1 ns */
40 /* PTP Timestamp control register defines */
49 /* Enable PTP packet Processing for Version 2 Format */
51 /* Enable Processing of PTP over Ethernet Frames */
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/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
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Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
114 return -EINVAL; in ice_ptp_set_sma_config_e810t()
119 return -EINVAL; in ice_ptp_set_sma_config_e810t()
179 * @info: the driver's PTP info structure
191 struct ice_hw *hw = &pf->hw; in ice_ptp_set_sma_e810t()
195 return -EOPNOTSUPP; in ice_ptp_set_sma_e810t()
220 * @info: the driver's PTP info structure
235 return -EOPNOTSUPP; in ice_verify_pin_e810t()
243 return -EOPNOTSUPP; in ice_verify_pin_e810t()
247 return -EOPNOTSUPP; in ice_verify_pin_e810t()
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/linux-6.12.1/drivers/ptp/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PTP clock support configuration
6 menu "PTP clock support"
9 tristate "PTP clock support"
17 standard defines a Precision Time Protocol (PTP), which can
23 This driver adds support for PTP clocks as character
24 devices. If you want to use a PTP clock, then you should
28 will be called ptp.
37 into vmlinux while the PTP support itself is in a loadable
39 If PTP support is disabled, this dependency will still be
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Dptp_qoriq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock for Freescale QorIQ 1588 timer
26 /* Caller must hold ptp_qoriq->lock. */
29 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_read()
33 lo = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_l); in tmr_cnt_read()
34 hi = ptp_qoriq->read(&regs->ctrl_regs->tmr_cnt_h); in tmr_cnt_read()
40 /* Caller must hold ptp_qoriq->lock. */
43 struct ptp_qoriq_registers *regs = &ptp_qoriq->regs; in tmr_cnt_write()
47 ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_l, lo); in tmr_cnt_write()
48 ptp_qoriq->write(&regs->ctrl_regs->tmr_cnt_h, hi); in tmr_cnt_write()
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Dptp_pch.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PTP 1588 clock using the EG20T PCH
6 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
15 #include <linux/io-64-nonatomic-lo-hi.h>
16 #include <linux/io-64-nonatomic-hi-lo.h>
43 * struct pch_ts_regs - IEEE 1588 registers
109 * struct pch_dev - Driver private data
124 * struct pch_params - 1588 module parameter
142 val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH); in pch_eth_enable_set()
143 iowrite32(val, (&chip->regs->ts_sel)); in pch_eth_enable_set()
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/linux-6.12.1/drivers/net/ethernet/cadence/
Dmacb_ptp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * 1588 PTP support for Cadence GEM device.
5 * Copyright (C) 2017 Cadence Design Systems - https://www.cadence.com
26 #define GEM_PTP_TIMER_NAME "gem-ptp-timer"
31 if (bp->hw_dma_cap == HW_DMA_CAP_PTP) in macb_ptp_desc()
34 if (bp->hw_dma_cap == HW_DMA_CAP_64B_PTP) in macb_ptp_desc()
41 static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts, in gem_tsu_get_time() argument
44 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info); in gem_tsu_get_time()
49 spin_lock_irqsave(&bp->tsu_clk_lock, flags); in gem_tsu_get_time()
59 /* if so, use later read & re-read seconds in gem_tsu_get_time()
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Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
100 #define GEM_RXPTPUNI 0x00D4 /* PTP RX Unicast address */
101 #define GEM_TXPTPUNI 0x00D8 /* PTP TX Unicast address */
102 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
103 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
104 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
105 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
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/linux-6.12.1/drivers/net/ethernet/mellanox/mlx4/
Den_clock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 /* mlx4_en_read_clock - read raw cycle counter (to be used by time counter)
45 struct mlx4_dev *dev = mdev->dev; in mlx4_en_read_clock()
47 return mlx4_read_clock(dev) & tc->mask; in mlx4_en_read_clock()
55 lo = (u64)be16_to_cpu(ts_cqe->timestamp_lo); in mlx4_en_get_cqe_ts()
56 hi = ((u64)be32_to_cpu(ts_cqe->timestamp_hi) + !lo) << 16; in mlx4_en_get_cqe_ts()
67 seq = read_seqbegin(&mdev->clock_lock); in mlx4_en_get_hwtstamp()
68 nsec = timecounter_cyc2time(&mdev->clock, timestamp); in mlx4_en_get_hwtstamp()
69 } while (read_seqretry(&mdev->clock_lock, seq)); in mlx4_en_get_hwtstamp()
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/linux-6.12.1/drivers/net/ethernet/xscale/
Dptp_ixp46x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock using the IXP46X
46 lo = __raw_readl(&regs->systime_lo); in ixp_systime_read()
47 hi = __raw_readl(&regs->systime_hi); in ixp_systime_read()
64 __raw_writel(lo, &regs->systime_lo); in ixp_systime_write()
65 __raw_writel(hi, &regs->systime_hi); in ixp_systime_write()
75 struct ixp46x_ts_regs *regs = ixp_clock->regs; in isr()
79 val = __raw_readl(&regs->event); in isr()
83 if (ixp_clock->exts0_enabled) { in isr()
84 hi = __raw_readl(&regs->asms_hi); in isr()
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/linux-6.12.1/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_ptp.c2 * cxgb4_ptp.c:Chelsio PTP support for T5/T6
4 * Copyright (c) 2003-2017 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
54 * cxgb4_ptp_is_ptp_tx - determine whether TX packet is PTP or not
55 * @skb: skb of outgoing ptp request
63 return skb->len >= PTP_MIN_LENGTH && in cxgb4_ptp_is_ptp_tx()
64 skb->len <= PTP_IN_TRANSMIT_PACKET_MAXNUM && in cxgb4_ptp_is_ptp_tx()
65 likely(skb->protocol == htons(ETH_P_IP)) && in cxgb4_ptp_is_ptp_tx()
66 ip_hdr(skb)->protocol == IPPROTO_UDP && in cxgb4_ptp_is_ptp_tx()
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/linux-6.12.1/drivers/net/ethernet/intel/e1000e/
Dptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfine - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
27 static int e1000e_phc_adjfine(struct ptp_clock_info *ptp, long delta) in e1000e_phc_adjfine() argument
29 struct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter, in e1000e_phc_adjfine()
31 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfine()
42 spin_lock_irqsave(&adapter->systim_lock, flags); in e1000e_phc_adjfine()
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/linux-6.12.1/drivers/net/ethernet/intel/igc/
Digc_ptp.c1 // SPDX-License-Identifier: GPL-2.0
27 struct igc_hw *hw = &adapter->hw; in igc_ptp_read()
34 ts->tv_sec = sec; in igc_ptp_read()
35 ts->tv_nsec = nsec; in igc_ptp_read()
41 struct igc_hw *hw = &adapter->hw; in igc_ptp_write_i225()
43 wr32(IGC_SYSTIML, ts->tv_nsec); in igc_ptp_write_i225()
44 wr32(IGC_SYSTIMH, ts->tv_sec); in igc_ptp_write_i225()
47 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm) in igc_ptp_adjfine_i225() argument
49 struct igc_adapter *igc = container_of(ptp, struct igc_adapter, in igc_ptp_adjfine_i225()
51 struct igc_hw *hw = &igc->hw; in igc_ptp_adjfine_i225()
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/linux-6.12.1/drivers/net/ethernet/renesas/
Drcar_gen4_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas R-Car Gen4 gPTP device driver
15 #define ptp_to_priv(ptp) container_of(ptp, struct rcar_gen4_ptp_private, info) argument
29 static int rcar_gen4_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) in rcar_gen4_ptp_adjfine() argument
31 struct rcar_gen4_ptp_private *ptp_priv = ptp_to_priv(ptp); in rcar_gen4_ptp_adjfine()
33 s64 addend = ptp_priv->default_addend; in rcar_gen4_ptp_adjfine()
37 scaled_ppm = -scaled_ppm; in rcar_gen4_ptp_adjfine()
39 addend = neg_adj ? addend - diff : addend + diff; in rcar_gen4_ptp_adjfine()
41 iowrite32(addend, ptp_priv->addr + ptp_priv->offs->increment); in rcar_gen4_ptp_adjfine()
47 static void _rcar_gen4_ptp_gettime(struct ptp_clock_info *ptp, in _rcar_gen4_ptp_gettime() argument
[all …]
Dravb_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* PTP 1588 clock using the Renesas Ethernet AVB
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
13 struct net_device *ndev = priv->ndev; in ravb_ptp_tcr_request()
27 struct net_device *ndev = priv->ndev; in ravb_ptp_time_read()
34 ts->tv_nsec = ravb_read(ndev, GCT0); in ravb_ptp_time_read()
35 ts->tv_sec = ravb_read(ndev, GCT1) | in ravb_ptp_time_read()
45 struct net_device *ndev = priv->ndev; in ravb_ptp_time_write()
55 return -EBUSY; in ravb_ptp_time_write()
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/linux-6.12.1/drivers/net/ethernet/freescale/enetc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
8 If compiled as module (M), the module name is fsl-enetc-core.
25 If compiled as module (M), the module name is fsl-enetc.
38 If compiled as module (M), the module name is fsl-enetc-vf.
46 If compiled as module (M), the module name is fsl-enetc-ierb.
55 If compiled as module (M), the module name is fsl-enetc-mdio.
58 tristate "ENETC PTP clock driver"
62 This driver adds support for using the ENETC 1588 timer
63 as a PTP clock. This clock is only useful if your PTP
64 programs are getting hardware time stamps on the PTP Ethernet
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/linux-6.12.1/arch/arm/boot/dts/intel/ixp/
Dintel-ixp45x-ixp46x.dtsi1 // SPDX-License-Identifier: ISC
8 #include "intel-ixp4xx.dtsi"
13 compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
19 compatible = "intel,ixp46x-rng";
23 interrupt-controller@c8003000 {
24 compatible = "intel,ixp43x-interrupt";
32 compatible = "intel,ixp4xx-udc";
39 compatible = "intel,ixp4xx-i2c";
47 compatible = "intel,ixp4xx-ethernet";
52 queue-rx = <&qmgr 0>;
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