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/linux-6.12.1/Documentation/devicetree/bindings/firmware/
Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx Network Processing Engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
29 - description: NPE0 (NPE-A) register range
[all …]
/linux-6.12.1/drivers/media/platform/renesas/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 tristate "Renesas Capture Engine Unit (CEU) driver"
18 tristate "R-Car MIPI CSI-2 Receiver"
27 Support for Renesas R-Car MIPI CSI-2 receiver.
28 Supports R-Car Gen3 and RZ/G2 SoCs.
31 module will be called rcar-csi2.
34 tristate "R-Car Image Signal Processor (ISP)"
43 Support for Renesas R-Car Image Signal Processor (ISP).
44 Enable this to support the Renesas R-Car Image Signal
48 module will be called rcar-isp.
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/gt/uc/
Dguc_capture_fwif.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2021-2022 Intel Corporation
18 * Book-keeping structure used to track read and write pointers
19 * as we extract error capture data from the GuC-log-buffer's
20 * error-capture region as a stream of dwords.
30 * struct __guc_capture_parsed_output - extracted error capture node
32 * A single unit of extracted error-capture output data grouped together
33 * at an engine-instance level. We keep these nodes in a linked list.
38 * A single set of 3 capture lists: a global-list
39 * an engine-class-list and an engine-instance list.
[all …]
/linux-6.12.1/Documentation/netlabel/
Dcipso_ipv4.rst2 NetLabel CIPSO/IPv4 Protocol Engine
12 The NetLabel CIPSO/IPv4 protocol engine is based on the IETF Commercial
15 (draft-ietf-cipso-ipsecurity-01.txt). While the IETF draft never made
16 it to an RFC standard it has become a de-facto standard for labeled
19 Outbound Packet Processing
22 The CIPSO/IPv4 protocol engine applies the CIPSO IP option to packets by
31 Inbound Packet Processing
34 The CIPSO/IPv4 protocol engine validates every CIPSO IP option it finds at the
44 The CIPSO/IPv4 protocol engine contains a mechanism to translate CIPSO security
56 CIPSO/IPv4 protocol engine supports this caching mechanism.
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
Dpipeline.json21 "PublicDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy",
24 "BriefDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy"
27 … all slots in the load-store issue queue are busy. This event counts the cycles where all slots in…
30 … all slots in the load-store issue queue are busy. This event counts the cycles where all slots in…
33 …ots in the data processing issue queue are busy. This event counts the cycles where all slots in t…
36 …ots in the data processing issue queue are busy. This event counts the cycles where all slots in t…
39 …tion for which all slots in the data engine issue queue are busy. This event is set every time tha…
42 …tion for which all slots in the data engine issue queue are busy. This event is set every time tha…
/linux-6.12.1/Documentation/devicetree/bindings/media/
Dti,vpe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DRA7x Video Processing Engine (VPE)
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
13 The Video Processing Engine (VPE) is a key component for image post
14 processing applications. VPE consist of a single memory to memory
20 const: ti,dra7-vpe
24 - description: The VPE main register region
[all …]
Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
17 processing, it successfully generates a corrected output image.
18 The engine can be used to perform scaling, cropping and pixel format
24 - nxp,imx8mp-dw100
[all …]
Drenesas,vsp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VSP Video Processing Engine
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The VSP is a video processing engine that supports up-/down-scaling, alpha
14 blending, color space conversion and various other image processing features.
15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
20 - enum:
21 - renesas,r9a07g044-vsp2 # RZ/G2L
[all …]
Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Video Decoder Engine
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
[all …]
/linux-6.12.1/arch/powerpc/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
14 - Little-endian
25 - AltiVec extensions
37 - AltiVec extensions
59 tristate "Hash functions: SHA-1"
62 SHA-1 secure hash algorithm (FIPS 180)
67 tristate "Hash functions: SHA-1 (SPE)"
70 SHA-1 secure hash algorithm (FIPS 180)
73 - SPE (Signal Processing Engine) extensions
76 tristate "Hash functions: SHA-224 and SHA-256 (SPE)"
[all …]
/linux-6.12.1/Documentation/admin-guide/media/
Dplatform-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
17 am437x-vpfe TI AM437x VPFE
18 aspeed-video Aspeed AST2400 and AST2500
19 atmel-isc ATMEL Image Sensor Controller (ISC)
20 atmel-isi ATMEL Image Sensor Interface (ISI)
24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
26 coda-vpu Chips&Media Coda multi-standard codec IP
29 exynos-fimc-is EXYNOS4x12 FIMC-IS (Imaging Subsystem)
30 exynos-fimc-lite EXYNOS FIMC-LITE camera interface
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-ope.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ope.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Output Processing Engine (OPE) is one of the AHUB client. It has
12 sub blocks for data processing.
15 - Jon Hunter <jonathanh@nvidia.com>
16 - Mohan Kumar <mkumard@nvidia.com>
17 - Sameer Pujar <spujar@nvidia.com>
20 - $ref: dai-common.yaml#
[all …]
Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
14 engine through ADMAIF.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
Dpipeline.json15 "PublicDescription": "Duration for which all slots in the Load-Store Unit are busy",
18 "BriefDescription": "Duration for which all slots in the Load-Store Unit are busy"
21 "PublicDescription": "Duration for which all slots in the load-store issue queue are busy",
24 "BriefDescription": "Duration for which all slots in the load-store issue queue are busy"
27 … "PublicDescription": "Duration for which all slots in the data processing issue queue are busy",
30 … "BriefDescription": "Duration for which all slots in the data processing issue queue are busy"
33 "PublicDescription": "Duration for which all slots in the Data Engine issue queue are busy",
36 "BriefDescription": "Duration for which all slots in the Data Engine issue queue are busy"
/linux-6.12.1/include/crypto/internal/
Dengine.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Crypto engine API
12 #include <crypto/engine.h>
22 * struct crypto_engine - crypto hardware engine
23 * @name: the engine name
24 * @idling: the engine is entering idle state
26 * @running: the engine is on working
27 * @retry_support: indication that the hardware allows re-execution
29 * crypto-engine, in head position to keep order
30 * @list: link with the global crypto engine list
[all …]
/linux-6.12.1/drivers/media/platform/ti/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
47 tristate "TI VPE (Video Processing Engine) driver"
57 Support for the TI VPE(Video Processing Engine) block
/linux-6.12.1/Documentation/crypto/
Dcrypto_engine.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Crypto Engine
7 --------
8 The crypto engine (CE) API is a crypto queue manager.
11 -----------
18 struct crypto_engine engine;
22 The crypto engine only manages asynchronous requests in the form of
25 using container_of. In addition, the engine knows nothing about your
26 structure "``struct your_tfm_ctx``". The engine assumes (requires) the placement
30 -------------------
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/linux-6.12.1/Documentation/devicetree/bindings/crypto/
Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel IXP4xx cryptographic engine
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
15 (Network Processing Engine). Since it is not a device on its own
21 const: intel,ixp4xx-crypto
23 intel,npe-handle:
[all …]
/linux-6.12.1/drivers/dma/ptdma/
Dptdma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * -- Based on the CCP driver
25 #include "../virt-dma.h"
94 #define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \
96 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
109 #define LSB_COUNT (LSB_END - LSB_START + 1)
124 * struct pt_passthru_engine - pass-through operation
133 * - bit_mod, byte_swap, src, dst, src_len
134 * - mask, mask_len if bit_mod is not PT_PASSTHRU_BITWISE_NOOP
145 * struct pt_cmd - PTDMA operation request
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dintel,ixp4xx-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
18 Processing Engine) and the IXP4xx Queue Manager to process
24 const: intel,ixp4xx-ethernet
30 queue-rx:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
[all …]
/linux-6.12.1/drivers/crypto/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 Some VIA processors come with an integrated crypto engine
21 (so called VIA PadLock ACE, Advanced Cryptography Engine)
39 called padlock-aes.
53 called padlock-sha.
56 tristate "Support for the Geode LX AES engine"
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
62 engine for the CryptoAPI AES algorithm.
65 will be called geode-aes.
87 - A pkey base and API kernel module (pkey.ko) which offers the
[all …]
/linux-6.12.1/drivers/crypto/gemini/
Dsl3516-ce.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
8 * Called either Crypto Acceleration Engine Module, Security Acceleration Engine
9 * or IPSEC module in the datasheet, it will be called Crypto Engine for short
17 #include <crypto/engine.h>
90 * struct sl3516_ce_descriptor - descriptor for CE operations
100 * struct desc_frame_ctrl - Information for the current descriptor
107 * @perr: Protocol error during processing this descriptor
108 * @derr: Data error during processing this descriptor
125 * struct desc_flag_status - flag for this descriptor
[all …]
/linux-6.12.1/crypto/
Dcrypto_engine.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Handle async block request by crypto hardware engine.
12 #include <crypto/internal/engine.h>
35 * crypto_finalize_request - finalize one request if the request is done
36 * @engine: the hardware engine
40 static void crypto_finalize_request(struct crypto_engine *engine, in crypto_finalize_request() argument
50 if (!engine->retry_support) { in crypto_finalize_request()
51 spin_lock_irqsave(&engine->queue_lock, flags); in crypto_finalize_request()
52 if (engine->cur_req == req) { in crypto_finalize_request()
53 engine->cur_req = NULL; in crypto_finalize_request()
[all …]
/linux-6.12.1/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
16 Accelerated Processing Unit
19 Application-Specific Integrated Circuit
25 Azalia (HD audio DMA engine)
36 * SOCCLK: GPU Engine Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
68 Display Controller Engine
108 Display Micro-Controller Unit
111 Display Micro-Controller Unit, version B
225 Transition-Minimized Differential Signaling
/linux-6.12.1/Documentation/devicetree/bindings/misc/
Dxlnx,sd-fec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cvetic, Dragan <dragan.cvetic@amd.com>
11 - Erim, Salih <salih.erim@amd.com>
14 The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
15 which provides high-throughput LDPC and Turbo Code implementations.
17 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
18 principally covers codes used by LTE. The FEC Engine offers significant
[all …]

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