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/linux-6.12.1/Documentation/devicetree/bindings/display/panel/
Dpanel-edp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-edp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
14 to a Embedded DisplayPort AUX bus (see display/dp-aux-bus.yaml) without
17 board, either for second-sourcing purposes or to support multiple SKUs
18 with different LCDs that hook up to a common board.
27 provided anywhere on the DP AUX bus is the power sequencing timings.
30 power on timings for any panels expected to be connected to a board are
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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dcs35l33.txt5 - compatible : "cirrus,cs35l33"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
15 - reset-gpios : gpio used to reset the amplifier
17 - interrupts : IRQ line info CS35L33.
18 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
26 - cirrus,ramp-rate : On power up, it affects the time from when the power
27 up sequence begins to the time the audio reaches a full-scale output.
28 On power down, it affects the time from when the power-down sequence
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Drealtek,rt1015.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jack Yu <jack.yu@realtek.com>
15 - realtek,rt1015
20 realtek,power-up-delay-ms:
21 description: Set a delay time for flush work to be completed,
26 - compatible
27 - reg
32 - |
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Dadi,adau7002.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADAU7002 Stereo PDM-to-I2S/TDM Converter
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13 - $ref: dai-common.yaml#
19 IOVDD-supply:
21 IOVDD power supply, if skipped then it is assumed that the supply pin is
24 wakeup-delay-ms:
26 Delay after power up needed for device to settle.
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/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple MMC power sequence provider
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 The purpose of the simple MMC power sequence provider is to supports a set
19 const: mmc-pwrseq-simple
21 reset-gpios:
27 at initialization and prior we start the power up procedure of the card.
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Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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/linux-6.12.1/Documentation/devicetree/bindings/mfd/
Drohm,bd71847-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ROHM BD71847 and BD71850 Power Management Integrated Circuit
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 BD71847AMWV and BD71850MWV are programmable Power Management ICs for powering
14 single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is
18 …s://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-appl…
19 …s://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-appl…
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Drohm,bd71837-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd71837-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ROHM BD71837 Power Management Integrated Circuit
10 - Matti Vaittinen <mazziesaccount@gmail.com>
13 BD71837MWV is programmable Power Management ICs for powering single-core,
14 dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is optimized for low
18 …s://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-appl…
35 clock-names:
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/linux-6.12.1/tools/power/pm-graph/
Dsleepgraph.83 sleepgraph \- Suspend/Resume timing analysis
21 Generates output files in subdirectory: suspend-yymmdd-HHMMSS
27 \fB-h\fR
30 \fB-v\fR
33 \fB-verbose\fR
36 \fB-config \fIfile\fR
39 \fB-m \fImode\fR
42 \fB-o \fIname\fR
46 e.g. suspend-{hostname}-{date}-{time}
48 \fB-rtcwake \fIt\fR | off
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DREADME8 pm-graph: suspend/resume/boot timing analysis tools
11 …Home Page: https://www.intel.com/content/www/us/en/developer/topic-technology/open/pm-graph/overvi…
13 Report bugs/issues at bugzilla.kernel.org Tools/pm-graph
14 - https://bugzilla.kernel.org/buglist.cgi?component=pm-graph&product=Tools
17 - Getting Started:
20 - Feature Summary:
21 https://www.intel.com/content/www/us/en/developer/topic-technology/open/pm-graph/features.html
23 - upstream version in git:
24 git clone https://github.com/intel/pm-graph/
27 - Overview
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/linux-6.12.1/drivers/phy/intel/
Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/delay.h>
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
80 /* Already finish power off above */ in keembay_emmc_phy_power()
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
109 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
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Dphy-intel-lgm-emmc.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/delay.h>
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
88 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
91 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
102 ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG, in intel_emmc_phy_power()
106 dev_err(&phy->dev, "caldone failed, ret=%d\n", ret); in intel_emmc_phy_power()
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/linux-6.12.1/Documentation/timers/
Dtimers-howto.rst2 delays - Information on the various kernel delay / sleep mechanisms
6 RightWay (TM) to insert a delay?"
14 ----------------
18 it really need to delay in atomic context?" If so...
21 You must use the `*delay` family of functions. These
24 the desired delay:
30 udelay is the generally preferred API; ndelay-level
31 precision may not actually exist on many non-PC devices.
38 NON-ATOMIC CONTEXT:
42 help the scheduler, power management, and just make your
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/linux-6.12.1/tools/power/pm-graph/config/
Dexample.cfg9 # sudo ./sleepgraph.py -config config/example.cfg
14 # ---- General Options ----
26 output-dir: suspend-{hostname}-{date}-{time}
49 # Enable/disable runtime suspend for all devices, restore all after test (default: no-action)
53 # Switch the display on/off for the test using xset (default: no-action)
57 # Print the status of the test run in the given file (default: no-action)
64 # ---- Advanced Options ----
67 # command: echo mem > /sys/power/state
85 # Back to Back Suspend Delay
86 # Time delay between the two test runs in ms (default: 0 ms)
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/linux-6.12.1/drivers/media/i2c/
Ddw9768.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/delay.h>
9 #include <media/v4l2-async.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-fwnode.h>
13 #include <media/v4l2-subdev.h>
16 #define DW9768_MAX_FOCUS_POS (1024 - 1)
24 * Ring control and Power control register
30 * 1: Power down mode
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/linux-6.12.1/include/linux/mfd/wm8994/
Dpdata.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm8994/pdata.h -- Platform data for WM8994
39 * panel provided by the WISCE - see http://www.wolfsonmicro.com/wisce/
52 * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/
64 * WISCE - see http://www.wolfsonmicro.com/wisce/
78 * multiband compressor configuration panel in WISCE - see
89 * multiband compressor configuration panel in WISCE - see
100 * the multiband compressor configuration panel in WISCE - see
109 * Microphone detection rates, used to tune response rates and power
129 * Default values for GPIOs if non-zero, WM8994_CONFIGURE_GPIO
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/linux-6.12.1/drivers/soc/bcm/brcmstb/pm/
Ds2-mips.S1 /* SPDX-License-Identifier: GPL-2.0-only */
38 * s3: I-Cache line size
51 /* Lock this asm section into the I-cache */
52 addiu t1, s3, -1
65 /* Lock the interrupt vector into the I-cache */
77 /* Power down request */
109 /* 1ms delay needed for stable recovery */
110 /* Use TIMER1 to count 1 ms */
119 /* Prepare delay */
123 /* 1ms delay */
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/linux-6.12.1/arch/arm64/boot/dts/allwinner/
Dsun50i-a64-pine64-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include "sun50i-a64-pine64.dts"
8 compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
14 pinctrl-names = "default";
15 pinctrl-0 = <&rgmii_pins>;
16 phy-mode = "rgmii-txid";
17 phy-handle = <&ext_rgmii_phy>;
22 ext_rgmii_phy: ethernet-phy@1 {
23 compatible = "ethernet-phy-ieee802.3-c22";
30 * Ethernet PHY needs 30ms to properly power up and some more
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/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsdm670-google-sargo.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device tree for Google Pixel 3a, adapted from google-blueline device tree,
4 * xiaomi-lavender device tree, and oneplus-common device tree.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
19 /delete-node/ &mpss_region;
20 /delete-node/ &venus_mem;
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Dsc7280-crd-r3.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include "sc7280-idp.dtsi"
11 #include "sc7280-idp-ec-h1.dtsi"
14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
15 compatible = "qcom,sc7280-crd",
16 "google,hoglin-rev3", "google,hoglin-rev4",
17 "google,piglin-rev3", "google,piglin-rev4",
25 stdout-path = "serial0:115200n8";
30 regulators-2 {
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Dsc7280-herobrine-crd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "sc7280-herobrine.dtsi"
11 #include "sc7280-herobrine-audio-wcd9385.dtsi"
12 #include "sc7280-herobrine-lte-sku.dtsi"
27 vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "vreg_edp_bl_crd";
32 enable-active-high;
33 pinctrl-names = "default";
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/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_pps.c1 // SPDX-License-Identifier: MIT
30 struct drm_i915_private *i915 = to_i915(display->drm); in pps_name()
31 struct intel_pps *pps = &intel_dp->pps; in pps_name()
34 switch (pps->pps_pipe) { in pps_name()
46 MISSING_CASE(pps->pps_pipe); in pps_name()
50 switch (pps->pps_idx) { in pps_name()
56 MISSING_CASE(pps->pps_idx); in pps_name()
67 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_lock()
71 * See intel_pps_reset_all() why we need a power domain reference here. in intel_pps_lock()
74 mutex_lock(&display->pps.mutex); in intel_pps_lock()
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/linux-6.12.1/drivers/gpu/drm/panel/
Dpanel-panasonic-vvx10f034n00.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/delay.h>
23 * When power is turned off to this panel a minimum off time of 500ms has to be
25 * track of earliest wakeup time and delay subsequent prepare call accordingly
47 return mipi_dsi_turn_on_peripheral(wuxga_nt->dsi); in wuxga_nt_panel_on()
54 return mipi_dsi_shutdown_peripheral(wuxga_nt->dsi); in wuxga_nt_panel_disable()
61 regulator_disable(wuxga_nt->supply); in wuxga_nt_panel_unprepare()
62 wuxga_nt->earliest_wake = ktime_add_ms(ktime_get_real(), MIN_POFF_MS); in wuxga_nt_panel_unprepare()
74 * If the user re-enabled the panel before the required off-time then in wuxga_nt_panel_prepare()
75 * we need to wait the remaining period before re-enabling regulator in wuxga_nt_panel_prepare()
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/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
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/linux-6.12.1/Documentation/hwmon/
Dmax31827.rst1 .. SPDX-License-Identifier: GPL-2.0
12 Addresses scanned: I2C 0x40 - 0x5f
20 Addresses scanned: I2C 0x40 - 0x5f
28 Addresses scanned: I2C 0x40 - 0x5f
34 - Daniel Matyas <daniel.matyas@analog.com>
37 -----------
40 between them is found in the default power-on behaviour of the chips. While the
52 hysteresis value: -40 and -30 degrees for under temperature alarm and +100 and
77 The conversions can be manual with the one-shot functionality and automatic with
83 - 64000 (ms) = 1 conv/64 sec
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